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41. 发明申请

US20120249227A1 VOLTAGE LEVEL GENERATOR CIRCUIT 审中-公开
标题翻译：电压电平发生器电路
公开(公告)号：US20120249227A1
公开(公告)日：2012-10-04
申请号：US13350795
申请日：2012-01-15
申请人： Ryo NAKAYAMA , Masaki Yoshinaga , Yoshitaka Abe , Kenji Hirayama , Yoshihiro Hayashi
发明人： Ryo NAKAYAMA , Masaki Yoshinaga , Yoshitaka Abe , Kenji Hirayama , Yoshihiro Hayashi
IPC分类号： G05F3/02
CPC分类号： G05F3/20
摘要： A voltage level generator circuit comprised of a fixed voltage generator unit for generating a first electrical current in a fixed quantity from a first supply voltage; a first current mirror circuit unit including a first thin-film NMOSFET and a second thin-film NMOSFET and that outputs a second electrical current proportional to the first electrical current; a protective circuit including: a third thin-film NMOSFET and a first thick-film PMOSFET utilized as a grounded gate for protecting the second thin-film NMOSFET, a first diode for preventing inverse current flow to the first supply, and a second diode for preventing the gate-source voltage of the third thin-film NMOSFET from reaching a negative electrical potential; and a second current mirror circuit for outputting a third electrical current proportional to the second electrical current; and a first Zener diode unit for generating a first fixed voltage from a third electrical current.
摘要翻译：一种电压电平发生器电路，包括：固定电压发生器单元，用于从第一电源电压产生固定量的第一电流; 第一电流镜电路单元，包括第一薄膜NMOSFET和第二薄膜NMOSFET，并且输出与第一电流成比例的第二电流; 保护电路，包括：第三薄膜NMOSFET和用作保护第二薄膜NMOSFET的接地栅极的第一厚膜PMOSFET，用于防止反向电流流向第一电源的第一二极管和用于防止第三薄膜NMOSFET的栅极 - 源极电压达到负电位; 以及第二电流镜电路，用于输出与第二电流成比例的第三电流; 以及用于从第三电流产生第一固定电压的第一齐纳二极管单元。

42. 发明申请

US20120228728A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20120228728A1
公开(公告)日：2012-09-13
申请号：US13399475
申请日：2012-02-17
申请人： Makoto UEKI , Naoya Inoue , Yoshihiro Hayashi
发明人： Makoto UEKI , Naoya Inoue , Yoshihiro Hayashi
IPC分类号： H01L29/82 , H01L21/8246
CPC分类号： H01L43/12 , H01L27/228 , H01L43/08
摘要： A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer.
摘要翻译：一种半导体器件，其中在包含在多层布线层中的布线层A中形成MRAM，所述MRAM具有与形成在布线层中并彼此绝缘的第一布线接触的至少两个第一磁化闭塞层，自由磁化层在平面图中与两个第一磁化钉扎层重叠，并与第一磁化钉扎层，位于自由磁化层上方的非磁性层和位于非磁性层上的第二磁化钉扎层连接。

43. 发明授权

US08250180B2 Content delivery apparatus and content delivery method using the same 有权
标题翻译：内容传送装置和使用其的内容传送方法
公开(公告)号：US08250180B2
公开(公告)日：2012-08-21
申请号：US12216208
申请日：2008-07-01
申请人： Yoshihiro Hayashi , Tadashi Takeuchi
发明人： Yoshihiro Hayashi , Tadashi Takeuchi
IPC分类号： G06F15/16
CPC分类号： H04N7/17318 , H04N21/21 , H04N21/23 , H04N21/262
摘要： A content delivery system includes a delivery server, a storage apparatus having a logical unit for storing data regarding content items, and a management apparatus having a content management unit for managing a delivery server. The delivery server includes a conversion unit and a delivery unit. The conversion units acquires original data regarding a content item from an external origin server in response to a content addition request from the content management unit, converts the original data to data for delivery, and stores the content data for delivery in the first logical unit. The delivery unit reads, in response to a content delivery request from the client, the data for delivery from the logical unit and transmits it to the client.
摘要翻译：内容传送系统包括传送服务器，具有用于存储关于内容项的数据的逻辑单元的存储装置，以及具有用于管理传送服务器的内容管理单元的管理装置。递送服务器包括转换单元和递送单元。转换单元响应于来自内容管理单元的内容添加请求从外部来源服务器获取关于内容项的原始数据，将原始数据转换为要传送的数据，并将用于传送的内容数据存储在第一逻辑单元中。交付单元响应于来自客户端的内容递送请求从逻辑单元读取用于传送的数据并将其发送给客户端。

44. 发明申请

US20120115253A1 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US20120115253A1
公开(公告)日：2012-05-10
申请号：US13373098
申请日：2011-11-04
申请人： Kishou Kaneko , Naoya Inoue , Yoshihiro Hayashi
发明人： Kishou Kaneko , Naoya Inoue , Yoshihiro Hayashi
IPC分类号： H01L43/12
CPC分类号： H01L23/552 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a semiconductor apparatus includes forming a semiconductor device on a principal surface of a substrate, in which the semiconductor device includes an interconnect layer, forming a buffer film which covers the semiconductor device and prevents diffusion of a magnetic material, and forming a magnetic shielding film which covers the buffer film and includes the magnetic material.
摘要翻译：一种半导体装置的制造方法，其特征在于，在基板的主面上形成半导体装置，所述半导体装置具有互连层，形成覆盖所述半导体装置的缓冲膜，防止磁性材料的扩散，形成覆盖缓冲膜并包括磁性材料的磁屏蔽膜。

45. 发明申请

US20110284991A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20110284991A1
公开(公告)日：2011-11-24
申请号：US13106590
申请日：2011-05-12
申请人： Kenichiro HIJIOKA , Ippei Kume , Naoya Inoue , Hiroki Shirai , Jun Kawahara , Yoshihiro Hayashi
发明人： Kenichiro HIJIOKA , Ippei Kume , Naoya Inoue , Hiroki Shirai , Jun Kawahara , Yoshihiro Hayashi
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/10894 , H01L21/76811 , H01L23/5223 , H01L27/10852 , H01L28/75 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.
摘要翻译：半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。

46. 外观设计

USD645838S1 Voice recording/reproducing device 有权
标题翻译：录音/再现装置
公开(公告)号：USD645838S1
公开(公告)日：2011-09-27
申请号：US29385020
申请日：2011-02-08
申请人： Yoshihiro Hayashi
设计人： Yoshihiro Hayashi

47. 外观设计

USD645367S1 Automated analyzer 有权
标题翻译：自动分析仪
公开(公告)号：USD645367S1
公开(公告)日：2011-09-20
申请号：US29376231
申请日：2010-10-04
申请人： Yoshihiro Hayashi , Shigeru Fujii
设计人： Yoshihiro Hayashi , Shigeru Fujii

48. 外观设计

USD635121S1 Voice recording/reproducing device 有权
公开(公告)号：USD635121S1
公开(公告)日：2011-03-29
申请号：US29368765
申请日：2010-08-30
申请人： Noriaki Takahashi , Yoshihiro Hayashi
设计人： Noriaki Takahashi , Yoshihiro Hayashi

49. 发明申请

US20100327409A1 SEMICONDUCTOR DEVICE COMPRISING CAPACITIVE ELEMENT 有权
标题翻译：包含电容元件的半导体器件
公开(公告)号：US20100327409A1
公开(公告)日：2010-12-30
申请号：US12864091
申请日：2009-01-22
申请人： Ippei Kume , Naoya Inoue , Yoshihiro Hayashi
发明人： Ippei Kume , Naoya Inoue , Yoshihiro Hayashi
IPC分类号： H01L29/92 , H01L21/314
CPC分类号： H01L28/60 , H01L21/28506 , H01L21/31637 , H01L21/32053 , H01L21/32105 , H01L23/5223 , H01L23/5283 , H01L23/5286 , H01L27/0688 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A capacitive element formed within a semiconductor device comprises an upper electrode, a capacitive insulating film containing an oxide and/or silicate of a transition metal element, and a lower electrode having a polycrystalline conductive film composed of a material having higher oxidation resistance than the transition metal element and an amorphous or microcrystalline conductive film formed below the polycrystalline conductive film.
摘要翻译：形成在半导体器件内的电容元件包括上电极，含有过渡金属元素的氧化物和/或硅酸盐的电容绝缘膜，以及具有多晶导电膜的下电极，所述多晶导体膜由比所述转变金属元素和形成在多晶导电膜下面的非晶或微晶导电膜。

50. 发明申请

US20100148171A1 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100148171A1
公开(公告)日：2010-06-17
申请号：US12654205
申请日：2009-12-14
申请人： Yoshihiro Hayashi , Naoya Inoue , Kishou Kaneko
发明人： Yoshihiro Hayashi , Naoya Inoue , Kishou Kaneko
IPC分类号： H01L29/24 , H01L21/336
CPC分类号： H01L21/76807 , H01L21/28282 , H01L21/76877 , H01L27/1225 , H01L27/124 , H01L29/24 , H01L29/242 , H01L29/41 , H01L29/42344 , H01L29/42352 , H01L29/4908 , H01L29/495 , H01L29/4966 , H01L29/518 , H01L29/66757 , H01L29/66969 , H01L29/78648 , H01L29/7869 , H01L29/792
摘要： A semiconductor device of the present invention has a first interconnect layer formed over the semiconductor substrate, and a semiconductor element; the first interconnect layer has an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer; the semiconductor element has a semiconductor layer, a gate insulating film, and a gate electrode; the semiconductor layer is positioned over the first interconnect layer; the gate insulating film is positioned over or below semiconductor layer; and the gate electrode is positioned on the opposite side of the semiconductor layer while placing the gate insulating film in between.
摘要翻译：本发明的半导体器件具有形成在半导体衬底上的第一互连层和半导体元件; 所述第一互连层具有绝缘层，以及填充在所述绝缘层的表面部分中的第一互连层; 半导体元件具有半导体层，栅极绝缘膜和栅电极; 半导体层位于第一互连层上方; 栅绝缘膜位于半导体层之上或之下; 并且栅极电极位于半导体层的相反侧，同时将栅极绝缘膜放置在其间。

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