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1. 外观设计

USD645367S1 Automated analyzer 有权
标题翻译：自动分析仪
公开(公告)号：USD645367S1
公开(公告)日：2011-09-20
申请号：US29376231
申请日：2010-10-04
申请人： Yoshihiro Hayashi , Shigeru Fujii
设计人： Yoshihiro Hayashi , Shigeru Fujii

2. 发明授权

US5731687A Generator assembly 失效
标题翻译：发电机总成
公开(公告)号：US5731687A
公开(公告)日：1998-03-24
申请号：US634277
申请日：1996-04-18
申请人： Tutomu Hirano , Shigeru Fujii , Masashi Nakamura
发明人： Tutomu Hirano , Shigeru Fujii , Masashi Nakamura
IPC分类号： F02B63/04 , F02B77/13 , H02K5/04
CPC分类号： F02B63/04 , F02B77/13 , F02B2063/045 , F02B63/044
摘要： In a generator assembly, outside air, taken from a suction hole into a fixed soundproof housing, is sucked into a portable engine generator covered by a soundproof case to operate an engine and cool the interior of the fixed soundproof housing. The exhaust gas of the engine and the cooling air of the soundproof case are exhausted outside through the exhaust air hole of the soundproof case and the external exhaust hole of the fixed soundproof housing without leaking into the fixed soundproof housing. Therefore, the portable engine generator can be operated while it remains housed within the fixed soundproof housing. The exhaust air duct of the portable engine generator and the communicating duct of the fixed soundproof housing are communicated in a state of close contact, at the time that the portable engine generator has been positioned by a positioning member provided in the fixed soundproof housing. The portable engine generator can be put into or out from the fixed soundproof housing and is guided and housed by wheel guide rails provided within the fixed soundproof housing.
摘要翻译：在发电机组件中，从抽吸孔取入固定隔音壳体的外部空气被吸入由隔音壳体覆盖的便携式发动机发电机中，以操作发动机并且冷却固定隔音壳体的内部。发动机的排气和隔音箱的冷却空气通过隔音壳体的排气孔和固定隔音壳体的外部排气孔排出外部，而不会泄漏到固定隔音壳体中。因此，便携式发动机发电机可以在其保持在固定隔音壳体内时被操作。便携式发动机发电机的排气风道和固定隔音壳体的连通管道在通过设置在固定隔音壳体中的定位构件定位的状态下以紧密接触的状态通信。便携式发电机可以从固定隔音壳体放入或导出，并由设在固定隔音壳体内的轮子导轨引导和收纳。

3. 发明授权

US5093611A Output circuit for portable generators 失效
标题翻译：便携式发电机的输出电路
公开(公告)号：US5093611A
公开(公告)日：1992-03-03
申请号：US554194
申请日：1990-07-17
申请人： Masashi Nakamura , Shigeru Fujii
发明人： Masashi Nakamura , Shigeru Fujii
IPC分类号： B23K9/10
CPC分类号： B23K9/10 , Y10T307/289
摘要： An output circuit for a portable generator having a plurality of output windings provided separately from each other, and control winding provided separately from the output windings. A plurality of thyristor bridge circuits each having thyristors are connected respectively to the output windings. A superposing circuit superposes outputs from the thyristor bridge circuits one upon another to provide a first superposed output voltage. A rectifier circuit is connected to the control winding. The rectifier circuit is disposed such that its output voltage is superposed upon the first superposed output voltage to provide a second superposed output voltage. A control circuit is responsive to the second superposed output voltage for concurrently controlling voltages applied respectively to the gates of the thyristors of the thyristor bridge circuits to thereby maintain the first superposed output voltage at a constant value. An FET is connected to the output of the superposing circuit, and is connectible in series to an external load, for controlling supply of current flowing through the FET to the external load. A current cut-off circuit detects overcurrent in the output circuit and operable, upon detection of the overcurrent, to cause the FET to be turned off to thereby cut off the supply of current to the external load.
摘要翻译：一种用于便携式发电机的输出电路，具有彼此分开设置的多个输出绕组，以及与输出绕组分开设置的控制绕组。各自具有晶闸管的多个晶闸管桥接电路分别连接到输出绕组。叠加电路将晶闸管桥接电路的输出叠加起来以提供第一叠加输出电压。整流电路连接到控制绕组。整流电路被布置成使得其输出电压叠加在第一叠加输出电压上以提供第二叠加输出电压。控制电路响应于第二重叠输出电压，以同时控制分别施加到晶闸管桥接电路的晶闸管的栅极的电压，从而将第一叠加输出电压保持在恒定值。 FET连接到叠加电路的输出端，可与外部负载串联连接，用于控制流过FET至外部负载的电流供应。电流截止电路检测输出电路中的过电流，并且在检测到过电流时可操作，以使FET截止，从而切断对外部负载的电流供应。

4. 发明授权

US3963803A Antistatic acrylic fiber 失效
标题翻译：防静电丙烯酸纤维
公开(公告)号：US3963803A
公开(公告)日：1976-06-15
申请号：US400207
申请日：1973-09-24
申请人： Hiroyoshi Tanaka , Haruo Obara , Teruo Koseki , Hajime Machida , Michihiko Tanaka , Shigeru Fujii
发明人： Hiroyoshi Tanaka , Haruo Obara , Teruo Koseki , Hajime Machida , Michihiko Tanaka , Shigeru Fujii
IPC分类号： C08L33/18 , C08L67/02 , D01F6/54 , C08G39/10
CPC分类号： D01F6/54 , C08L33/18 , C08L67/025 , Y10S260/17
摘要： An acrylic fiber having excellent antistatic properties is obtained by mixing a polymer (A) consisting mainly of acrylonitrile with a copolymer (B) consisting mainly of a polyetherpolyester block copolymer consisting of a polyester and compound represented by the general formula (1): ##EQU1## (wherein each of m and n is O or a positive integer, wherein 25 .ltoreq. m + n .ltoreq. 1000, and m .gtoreq. 10).
摘要翻译：通过将主要由丙烯腈组成的聚合物（A）与主要由聚酯和由通式（1）表示的化合物组成的聚醚聚酯嵌段共聚物共聚物（B））混合得到具有优异抗静电性能的丙烯酸纤维：CH3 | HO-CH 2 CH 2 O）m - （CH 2 CH.OnH（1）（其中m和n分别为O或正整数，其中25≤m+ n <1000，m> = 10）。

5. 发明申请

US20080227226A1 Semiconductor substrate, manufacturing method of a semiconductor device and testing method of a semiconductor device 审中-公开
标题翻译：半导体衬底，半导体器件的制造方法和半导体器件的测试方法
公开(公告)号：US20080227226A1
公开(公告)日：2008-09-18
申请号：US12153481
申请日：2008-05-20
申请人： Shigeru Fujii , Yoshikazu Arisaka , Hitoshi Izuru , Kazuhiro Tashiro , Shigeyuki Maruyama
发明人： Shigeru Fujii , Yoshikazu Arisaka , Hitoshi Izuru , Kazuhiro Tashiro , Shigeyuki Maruyama
IPC分类号： H01L21/66 , H01L21/304
CPC分类号： H01L21/78 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the semiconductor element areas. A first scribe line extends between the semiconductor element areas formed within the unit exposed and printed area. A second scribe line extends between the unit exposed and printed areas. A width of the first scribe line is different from a width of the second scribe line.
摘要翻译：半导体衬底消除了由划线的宽度引起的限制，从而增加形成在半导体衬底上的半导体元件的数量。多个半导体元件区域通过形成多个单位曝光和印刷区域而形成，每个单元暴露和印刷区域都包含半导体元件区域。第一刻划线在形成在单元曝光和印刷区域内的半导体元件区域之间延伸。第二划线在单元曝光和打印区域之间延伸。第一划线的宽度与第二划线的宽度不同。

6. 发明授权

US5489860A Semiconductor circuit having improved layout pattern 失效
标题翻译：具有改进布局图案的半导体电路
公开(公告)号：US5489860A
公开(公告)日：1996-02-06
申请号：US138081
申请日：1993-10-20
申请人： Masaya Kitagawa , Shigeru Fujii
发明人： Masaya Kitagawa , Shigeru Fujii
IPC分类号： H01L27/118 , H01L25/00
CPC分类号： H01L27/11807
摘要： A semiconductor circuit includes a plurality of first power supply lines which are arranged parallel to each other, a plurality of second power supply lines which are arranged parallel to each other and supplying a power supply voltage different from that supplied by the first power supply lines, where the first and second power supply lines run parallel to each other in a first direction, a first cell made up of the same number of first p-channel transistors and first n-channel transistors which are respectively coupled to the first and second power supply lines, where the first p-channel transistors and the first n-channel transistors are alternately arranged in a second direction and have the same size, and a second cell made up of a different number of second p-channel transistors and second n-channel transistors which are respectively coupled to the first and second power supply lines. The second p-channel transistors and the second n-channel transistors are alternately arranged in the second direction, and the second p-channel transistors are electrically coupled in parallel, so that the second p-channel transistors have a predetermined driving capability.
摘要翻译：半导体电路包括彼此平行布置的多个第一电源线，多个第二电源线，彼此并联布置并提供与由第一电源线提供的电源电压不同的电源电压，其中第一和第二电源线在第一方向上彼此平行地延伸，由相同数量的第一p沟道晶体管和第一n沟道晶体管组成的第一单元，第一p沟道晶体管和第一n沟道晶体管分别耦合到第一和第二电源线，其中第一p沟道晶体管和第一n沟道晶体管沿第二方向交替布置并具有相同的尺寸，以及由不同数量的第二p沟道晶体管和第二n沟道晶体管构成的第二单元分别耦合到第一和第二电源线的晶体管。第二p沟道晶体管和第二n沟道晶体管沿第二方向交替布置，并且第二p沟道晶体管并联电耦合，使得第二p沟道晶体管具有预定的驱动能力。

7. 发明授权

US4701777A Gate array type semiconductor integrated circuit device 失效
标题翻译：门阵列型半导体集成电路器件
公开(公告)号：US4701777A
公开(公告)日：1987-10-20
申请号：US948406
申请日：1986-12-30
申请人： Yoshihisa Takayama , Shigeru Fujii , Tomoaki Tanabe
发明人： Yoshihisa Takayama , Shigeru Fujii , Tomoaki Tanabe
IPC分类号： H01L27/08 , H01L21/82 , H01L21/8234 , H01L27/088 , H01L27/092 , H01L27/118 , H01L27/02 , G11C5/02 , H01L27/10 , H01L27/15
CPC分类号： H01L27/0921 , H01L21/82 , H01L27/11807
摘要： A gate array type semiconductor device including at least a plurality of basic cell arrays and diffusion regions for suppressing latchup in the basic cells forming the basic cell arrays. Each of the diffusion regions has a comb-shaped structure, i.e., wide tooth parts, narrow tooth parts, and a base part, formed as an integral structure. These parts partially surround each basic cell.
摘要翻译：一种栅极阵列型半导体器件，包括至少多个基本单元阵列和用于抑制形成基本单元阵列的基本单元中的锁存的扩散区域。每个扩散区具有梳状结构，即形成为整体结构的宽齿部，窄齿部和基部。这些部分部分围绕每个基本单元。

8. 发明授权

US07251638B2 Intelligent robust control system for motorcycle using soft computing optimizer 失效
标题翻译：使用软计算优化器的摩托车智能鲁棒控制系统
公开(公告)号：US07251638B2
公开(公告)日：2007-07-31
申请号：US10792292
申请日：2004-03-03
申请人： Shigeru Fujii , Hitoshi Watanabe , Sergey A. Panfilov , Kazuki Takahashi , Sergey V. Ulyanov
发明人： Shigeru Fujii , Hitoshi Watanabe , Sergey A. Panfilov , Kazuki Takahashi , Sergey V. Ulyanov
IPC分类号： G05B13/00 , G05B13/04 , G05B15/00
CPC分类号： B62K21/00
摘要： A Soft Computing (SC) optimizer for designing a Knowledge Base (KB) to be used in a control system for controlling a motorcycle is described. In one embodiment, a simulation model of the motorcycle and rider control is used. In one embodiment, the simulation model includes a feedforward rider model. The SC optimizer includes a fuzzy inference engine based on a Fuzzy Neural Network (FNN). The SC Optimizer provides Fuzzy Inference System (FIS) structure selection, FIS structure optimization method selection, and teaching signal selection and generation. The user selects a fuzzy model, including one or more of: the number of input and/or output variables; the type of fuzzy inference; and the preliminary type of membership functions. A Genetic Algorithm (GA) is used to optimize linguistic variable parameters and the input-output training patterns. A GA is also used to optimize the rule base, using the fuzzy model, optimal linguistic variable parameters, and a teaching signal. The GA produces a near-optimal FNN. The near-optimal FNN can be improved using classical derivative-based optimization procedures. The FIS structure found by the GA is optimized with a fitness function based on a response of the actual plant model of the controlled plant. The SC optimizer produces a robust KB that is typically smaller that the KB produced by prior art methods.
摘要翻译：描述了用于设计用于控制摩托车的控制系统中使用的知识库（KB）的软计算（SC）优化器。在一个实施例中，使用摩托车和骑手控制的仿真模型。在一个实施例中，模拟模型包括前馈骑手模型。 SC优化器包括基于模糊神经网络（FNN）的模糊推理机。 SC优化器提供模糊推理系统（FIS）结构选择，FIS结构优化方法选择和教学信号选择与生成。用户选择模糊模型，包括以下一个或多个：输入和/或输出变量的数量; 模糊推理的类型; 和初步类型的会员职能。遗传算法（GA）用于优化语言变量参数和输入 - 输出训练模式。 GA也用于优化规则库，使用模糊模型，最优语言变量参数和教学信号。 GA产生近乎最佳的FNN。可以使用经典的基于导数的优化程序来改进近似最优的FNN。 GA发现的FIS结构通过基于受控植物实际植物模型的响应的适应度函数进行优化。 SC优化器产生通常比现有技术方法产生的KB更小的鲁棒KB。

9. 发明授权

US5132563A LSI gate array having reduced switching noise 失效
标题翻译：具有降低开关噪音的LSI门阵列
公开(公告)号：US5132563A
公开(公告)日：1992-07-21
申请号：US746158
申请日：1991-08-14
申请人： Shigeru Fujii , Kouichi Yamashita , Tomoaki Tanabe , Yoshio Kuniyasu
发明人： Shigeru Fujii , Kouichi Yamashita , Tomoaki Tanabe , Yoshio Kuniyasu
IPC分类号： H01L21/8234 , H01L21/82 , H01L27/088 , H01L27/118 , H03K19/003 , H03K19/08
CPC分类号： H03K19/00361 , H01L27/11807
摘要： As the number of output circuits in LSI or VLSI circuits increases, the chance of many large output circuits operating as a same instant increases, which can cause a malfunction in the logic due to induced switching noise. In order to prevent such a problem, the switching speed of the driving buffer circuit for an output buffer circuit is controlled. By reducing the switching capacity of the driving circuit, the switching speed of the total circuit is not greatly affected and the noise is greatly decreased. Control of the switching capacity of the driving buffer circuit is performed by master slice technology. This opposite design concept, compared to that of prior art LSI design, has been proved by experiments.

10. 发明授权

US4700089A Delay circuit for gate-array LSI 失效
标题翻译：门阵列LSI延时电路
公开(公告)号：US4700089A
公开(公告)日：1987-10-13
申请号：US767574
申请日：1985-08-20
申请人： Shigeru Fujii , Masanori Oozeki
发明人： Shigeru Fujii , Masanori Oozeki
IPC分类号： H03K5/00 , H03K5/13 , H03K19/094 , H03K3/353 , H03K17/284 , H03K17/687
CPC分类号： H03K5/133 , H03K2005/00215
摘要： A delay circuit for a gate-array LSI including at least one inverter having a plurality of P-channel transistors (Q.sub.1p to Q.sub.4p) and a plurality of N-channel transistors (Q.sub.1n to Q.sub.4n) connected in series. The P-channel/N-channel transistors are driven by an input potential (IN), and the common output of the innermost pair of P-channel/N-channel transistors generates an output.
摘要翻译：包括具有串联连接的多个P沟道晶体管（Q1p〜Q4p）和多个N沟道晶体管（Q1n〜Q4n）的至少一个反相器的栅极阵列LSI的延迟电路。 P沟道/ N沟道晶体管由输入电位（IN）驱动，最里面的P沟道/ N沟道晶体管对的公共输出产生输出。

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