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41. 发明专利

JPH02112054A DATA PROCESSOR 失效
公开(公告)号：JPH02112054A
公开(公告)日：1990-04-24
申请号：JP26390288
申请日：1988-10-21
申请人： HITACHI LTD
发明人： OGURA TOSHIHIKO , IKEDA NAOYA , SASAKI HISAO , HOTTA ATSUO
IPC分类号： G06F15/16 , G06F15/177
摘要： PURPOSE:To exchange data between processors at a high speed by providing plural registers for storing data to be processed, operator for performing arithmetic operations and control circuit for controlling execution of instructions and constituting parts of the plural resistors of FIFO (first in first out) memories. CONSTITUTION:This data processor is constituted of a control circuit 1 which controls the execution of the processor, register 2, operator 3, read FIFO memory 4, write FIFO memory 5, and program memory 6. Since the FIFO memories connected at an equivalent level to registers can treat data at an inter-register operating speed, the data transferring speed to another data processor can be improved by the ratio of the speed of operating instructions to registers and memories to the speed of inter-register operation instructions. Therefore, operating time of this multiprocessor system can be improved, since data transfer between data processors of the system can be performed within the execution time of an inter-register transfer instruction.

42. 发明专利

JPH0214322A PROGRAM CONTROL CIRCUIT 失效
公开(公告)号：JPH0214322A
公开(公告)日：1990-01-18
申请号：JP16252088
申请日：1988-07-01
申请人： HITACHI LTD
发明人： OGURA TOSHIHIKO , IKEDA NAOYA
IPC分类号： G06F9/42
摘要： PURPOSE:To improve the performance of a program by applying the built-in stack of a high speed to a part, where an access frequency is high. CONSTITUTION:A program control circuit normally uses an external stack. When a stack operation instruction is executed, since the output of an OR gate 103 goes to be 1 and the output of a NOT gate 113 is 1, the output of an AND gate 107 goes to be 1 and a latch L2 goes to be 1. With receiving such an output, a memory select signal MS of a memory interface 16 goes to be 1 and a memory access is executed. Then, the normal operation of a memory stack is realized. Here, when a stack switching sub routine call XCALL is executed, a latch signal L4 goes to be 1 and the value of an external stack pointer 8 is latched to a work pointer 10. A flip-flop 110 goes to be 1 and the output of an EOR gate 112 goes to be 1. Then, the outputs of OR gates 103 and 104 go to be 1 and a stack control signal is switched to a built-in stack 6 by AND gates 105 and 106.

43. 发明专利

JPS63210680A INPUT VECTOR SUPPLY CIRCUIT FOR PHYSICAL MODEL 失效
公开(公告)号：JPS63210680A
公开(公告)日：1988-09-01
申请号：JP4152987
申请日：1987-02-26
申请人： HITACHI LTD
发明人： IKEDA NAOYA , KIMURA KOICHI , OKAZAKI YOSHINOBU
IPC分类号： G01R31/28 , G06F17/50
摘要： PURPOSE:To enable the lowering of memory capacity, by selecting full-size chip input signal information from a memory output from terminal connection information to eliminate the need for allotting a history memory to all of external of a full-size chip. CONSTITUTION:A pin assigning register 21 stores in a binary code whether any one of outputs of m-bit history memories 4 should be selected through a pin assigning information signal bus 20 from a host computer or not input signal is needed. A decoding circuit 22 compounds a m-bit selection signal to select a history memory output from pin assigning information and an input cutting signal 24 to indicate the unnecessariness of an input signal. Then, a driver element 25 supplies an output as high impedance in the state thereof to a pin corresponding to a full-size chip 6 when the input cutting signal 24 is at a high level and 1 bit of an output of the history memory selected with a selector circuit 23 thereto as input signal when it 24 is at a low level.

44. 发明专利

JPS6398043A OUTPUT SIGNAL DETECTION CIRCUIT 失效
公开(公告)号：JPS6398043A
公开(公告)日：1988-04-28
申请号：JP24290686
申请日：1986-10-15
申请人： HITACHI LTD
发明人： IKEDA NAOYA , KIMURA KOICHI , OKADA KUNIHIRO , OKAZAKI YOSHINOBU
IPC分类号： G06F11/25 , G06F11/26 , G06F17/50
摘要： PURPOSE:To prevent the power consumption of a real chip from being increased, and an element from being damaged, by providing a fixed power source voltage circuit, and an intermediate voltage supplying circuit, in the detection circuit of a real chip output signal. CONSTITUTION:A power source voltage outputted from the fixed power source voltage supplying circuit 100, and an intermediate voltage outputted from the intermediate voltage supplying circuit 101, are selected at a selection circuit 102, and at a time when a signal path 24 becomes the output signal path of the real chip 6, a selected voltage is supplied to the signal path 24. And at the time when the power source voltage is supplied to the signal path 24, the signal path 24, therefore, the outside terminal of the real chip 6 go to the potential of an H level, or an L level. Also, when the intermediate voltage is supplied to the signal path 24, the signal path 24, therefore, the outside terminal of the real chip 6 go to the intermediate potential of the H level and the L level. In this way, it is possible to prevent the power consumption of the real chip from being increased even the chip has CMOS structure, and the element from being damaged.

45. 发明专利

JPS62276636A MEMORY CONTROL CIRCUIT 失效
公开(公告)号：JPS62276636A
公开(公告)日：1987-12-01
申请号：JP11918786
申请日：1986-05-26
申请人： HITACHI LTD
发明人： IKEDA NAOYA , KIMURA KOICHI , OKAZAKI YOSHINOBU
IPC分类号： G06F11/25 , G06F11/26 , G06F17/50
摘要： PURPOSE:To remarkably shorten data writing in a memory by allowing banks in a history memory to be writable status in order at the time of writing the input vectors in the history memory divided in each bank. CONSTITUTION:A bank switching means 26 consists of a counter 27 and a demultiplexer 28 and outputs a bank selecting signal A for switching respective banks 1, 2,..., t in the history memory 4 in order. The counter 27 counts up a memory write signal M supplied from a host computer 1 through a control line 13. The demultiplexer 28 decodes the count value (n) of the counter 27 and forms and outputs he bank selecting signal A consisting of (t) bits for allowing any one of the banks 1-t in the memory 4 to be writable status. Namely, the count value (n) of the counter 27 corresponds to any one of the banks 1-n.

46. 发明专利

JPS62228179A INPUT VECTOR TRAIN DRIVING SYSTEM 失效
公开(公告)号：JPS62228179A
公开(公告)日：1987-10-07
申请号：JP6981586
申请日：1986-03-29
申请人： HITACHI LTD
发明人： KIMURA KOICHI , AOTSU HIROAKI , MORITA MASATO , OKAZAKI YOSHINOBU , IKEDA NAOYA
IPC分类号： G01R31/302 , G01R31/28
摘要： PURPOSE:To enable the use of a small capacity low speed vector memory and to enable the stable operation of a LSI chip being a simulation object, by forming a lead signal and a second reference clock, etc. on the basis of a reference clock by a control part according to a hardware system. CONSTITUTION:When a start signal X is applied from a host calculator 1, the frequency of a reference clock phiC is divided by a control part 4 to form a second reference clock CLK and a read signal RD having phase difference such as one cycle of the clock phiC with respect to said clock CLK. Simulation input is read from a vector memory 3 corresponding to the signal RD to be supplied to a LSI chip 2 controlled by the clock CLK. By the formation of the clock CLK and the read signal RD by a hardware, a reference clock is stabilized and formed by a forming source different from an input vector train forming source and the phase difference thereof can be set to a predetermined value without increasing vector quantity. By this constitution, the capacity of the vector memory can be reduced and the speed thereof is decreased and LSI being a simulation object operates stably.

47. 发明专利

JPS62139052A PREVENTING SYSTEM FOR DESTRUCTION OF ELEMENT 失效
公开(公告)号：JPS62139052A
公开(公告)日：1987-06-22
申请号：JP27896785
申请日：1985-12-13
申请人： HITACHI LTD
发明人： KIMURA KOICHI , AOTSU HIROAKI , MORITA MASATO , OKAZAKI YOSHINOBU , IKEDA NAOYA
IPC分类号： G06F11/26 , G06F11/00 , G06F17/50
摘要： PURPOSE:To prevent the destruction of an LSi chip by detecting and deciding previously the collision between the (n+1)-th input vector and the output signal sent from the LSi chip in an execution mode of simulations up the (n+1)-th one. CONSTITUTION:In case the (n+1)-th vectors Mo0 and Mo1 are applied as the input vector iN, the read/write signal R/W has a writing action in the next (n+1) cycle. Thus the output Mo0 of a vector memory Mv0 must be equal to 0. Thus the collision of signals can be detected previously in the next (n+1)-th cycle by comparing the output Z of a detecting circuit ZD5 with the signal W/R through a comparator CMP6 at a time point tD, for example, when the signal W/R is fixed after the n-th simulation. Here the comparator CMP6 compares the output Z of the ZD5 with the signal W/R, for example, at the time point tD to detect previously the presence or absence of the collision between the input vector and the output signal sent from an LSi chip.

48. 发明专利

JPS6278619A KEY INPUT DEVICE 失效
公开(公告)号：JPS6278619A
公开(公告)日：1987-04-10
申请号：JP21787885
申请日：1985-10-02
申请人： HITACHI LTD
发明人： IKEDA NAOYA , NAKANE KEIICHI , YOKOYAMA YOSHIHIRO , KOREEDA HIROYUKI
IPC分类号： G06F3/023 , H03M11/14
摘要： PURPOSE:To prevent the generation of an image key when >=3 keys are pushed at a time with no increase of the parts of a key input device, by using a specific control key switch and a scan signal inhibiting circuit. CONSTITUTION:A control key switch 100 attains a special function that is actuated only in combination with another key switch. Those key switches which are combined with the switch 100 for the special function are all positioned at their due positions on a scan line 15. In addition, a scan signal inhibiting circuit 103 is provided to the scan line 15 to inhibit the scan output signal 104 of a decoder 6 to the line 15 while the switch 100 is not pushed. Thus the generation of an image key is prevented in case >=3 keys are pushed at a time.

49. 发明专利

JPS6011919A INFORMATION PROCESSOR 失效
公开(公告)号：JPS6011919A
公开(公告)日：1985-01-22
申请号：JP11833983
申请日：1983-07-01
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： IKEDA NAOYA , TSUCHIYA NOBUO
IPC分类号： G06F3/02
摘要： PURPOSE:To obtain a simple and inexpensive information processor by changing the processing function in response to the number of pulses of the pulse signal sent from the CPU side while a change command signal is transmitted to a key input device. CONSTITUTION:A keyboard controller 5 of a key input circuit 4 transmits the key code data signal to a CPU1. The CPU1 detects thekey code through a main processor 6 and performs the arithmetic processing. A clock signal input terminal 19 of the CPU1 is connected to an external interruption terminal 29 of the controller 5 so that the same signal is supplied to both terminals. When data is delivered to a key input device from the CPU1, the signals of low levels (change command signals) are delivered to a clock signal line 15 from the processor 6 just for time t0. Thus an external interruption is applied to the controller 5, and the data is transmitted to the controller 5 in plural times. Then the pulses of low levels are transmitted to a data signal line 16 in the number of times equal to said data transmitting frequency.

50. 发明专利

JP2010110023A Information relay apparatus and transfer method 有权
标题翻译：信息中继装置和传送方法
公开(公告)号：JP2010110023A
公开(公告)日：2010-05-13
申请号：JP2010033506
申请日：2010-02-18
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAINOMOTO YOSHITAKA , HIGUCHI HIDEMITSU , IKEDA NAOYA , YOSHINO SHIGEKI , INAGAKI YUKIHIDE
IPC分类号： H04L12/701 , H04L12/775
摘要： PROBLEM TO BE SOLVED: To apply processing, regarding various additional functions, to an IP packet while improving the performance and reducing the load. SOLUTION: In a routing module 2, first transmission route information is obtained by retrieving a route information table from a reception packet from a low-order bus transmitting/receiving section 19, a route retrieval section 17 stores the obtained information in an identifier; a packet detection section 21 retrieves a detection condition table 22, corresponding to the predetermined retrieval conditions for obtaining second transmission route information containing a module number of a function extension module 6 for applying additional function processing to the reception packet; and a route information rewriting section 20 rewrites the first transmission route information in the identifier into the second transmission route information. In the function extension module 6, a reception packet is transferred from a higher-order bus transmitting/receiving section 9, a distribution section 8 transfers the reception packet to a function execution module 7, additional processing is applied therein, and a re-routing processing section 27 determines a transmission route of the packet after processing. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：在提高性能和减少负载的同时，将关于各种附加功能的处理应用于IP包。解决方案：在路由模块2中，通过从低层总线发送/接收部分19的接收分组检索路由信息表获得第一传输路由信息，路由检索部分17将所获得的信息存储在标识符; 分组检测部分21检索对应于预定检索条件的检测条件表22，用于获得包含用于对接收分组进行附加功能处理的功能扩展模块6的模块号的第二传输路由信息; 并且路线信息重写部分20将标识符中的第一传输路由信息重写为第二传输路由信息。在功能扩展模块6中，从高阶总线发送/接收部分9传送接收分组，分配部分8将接收分组传送到功能执行模块7，在其中应用附加处理，并且重新路由处理部分27确定处理之后的分组的传输路由。版权所有（C）2010，JPO＆INPIT

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