专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明专利

JPH11166961A BOUNDARY SCANNING CIRCUIT 失效
公开(公告)号：JPH11166961A
公开(公告)日：1999-06-22
申请号：JP35246697
申请日：1997-12-05
申请人： HITACHI LTD , HITACHI INFORMATION TECHNOLOGY
发明人： IZAKI KOJI , TAKAHASHI TETSUYA , YAMAGATA MAKOTO
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22
摘要： PROBLEM TO BE SOLVED: To reduce the overhead of a boundary scanning circuit in an LSI circuit being mounted to a JTAB circuit to a chip area. SOLUTION: One pair (1D, C1) of FF 59C of a user logic being arranged immediate after an LSI pin with two sets (1D/C1 and 2D/C2) of a pair of an input signal terminal and a clock signal input terminal is used for data input for user logic and for a system clock, the other pair (2D, C2) is used for scan data and a scan clock and a user logic FF is used also as a conventional register for updating, a boundary scan data that are transferred from a master register 59a for shifting to a slave register 59b for shifting on boundary scanning is inputted, and LSI scan in data that are inputted from an LSI pin to an FF 59C terminal 1D and are outputted from the FF output terminal are selected by a control circuit 60 according to an LSI scan mode signal 53 and are inputted to the register 59a.

42. 发明专利

JPH1183949A SEMICONDUCTOR INTEGRATED-CIRCUIT DEVICE 失效
公开(公告)号：JPH1183949A
公开(公告)日：1999-03-26
申请号：JP24127797
申请日：1997-09-05
申请人： HITACHI LTD , HITACHI INFORMATION TECHNOLOGY
发明人： TAKAHASHI TETSUYA , YAMAGATA MAKOTO
IPC分类号： G01R31/28
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor integrated-circuit device in which an increase in a wiring pattern amount is reduced by a method wherein a scan-in/ scan-out control circuit is controlled by a joint-test-action-group(JTAG) circuit control edge pin via a scan control circuit. SOLUTION: In a scan-in operation, scan-in control condition data is set at a scan control register 21 from a test data input(TDI) pin 14, control data is sent out to a scan-in/scan-out control circuit 19, and the scan-in operation is performed to an FF, to be scanned, in an FF group 10 to be scanned. In a scan-out operation, scan-out control condition data is set at a scan control register 21 from the TDI pin 14, control data is sent out to the scan-in/scan-out control circuit 19, and the FF, to be scanned, in the FF group 10 to be scanned is scan-out-controlled.

43. 发明专利

JPH07129426A FAULT PROCESSING SYSTEM 失效
公开(公告)号：JPH07129426A
公开(公告)日：1995-05-19
申请号：JP29460993
申请日：1993-10-29
申请人： HITACHI LTD
发明人： FUJIWARA HIROO , YAMAGATA MAKOTO
IPC分类号： G06F11/18 , G06F11/00 , G06F11/16
摘要： PURPOSE:To detect a data fault at any arbitrary place inside a chip in synchronism with the generation of the fault without providing any parity checker. CONSTITUTION:The arbitrary parts inside a processor are exclusively ORed by EOR circuits 5-1 and 5-2 and outputted to the outside as an internal state signal. This signal is exchanged between a master chip 1 and a slave chip and compared by a state comparator 8. When the states are not matched as a result of comparison, the update of internal resources is suppressed at both the chips, an interruption control circuit 11 is energized, and fault interruption is generated. Together with the generation of interruption, a master checker operation is started again.

44. 发明专利

JPH04365145A MEMORY FAULT PROCESSING METHOD 失效
公开(公告)号：JPH04365145A
公开(公告)日：1992-12-17
申请号：JP14157891
申请日：1991-06-13
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： SUGIOKA MASAYUKI , YAMAGATA MAKOTO , KOBAYASHI TAKASHI
IPC分类号： G06F11/34 , G06F12/16
摘要： PURPOSE:To quickly recover memory fault by storing system information, which is stored in a second memory, in the system information area of a first memory by the microprogram control to improve fault recovery, fault position indication, and log information gathering methods. CONSTITUTION:The memory area of an internal memory unit 11 in a data processor 10 is divided into a system information area where system information is stored and a data processing information area (these areas are omitted in the figure). Information having the same contents as this system information is stored in an internal memory work area 23 of a main storage device 20. When detecting the occurrence of fault in the memory write control during the data processing, the data processor 10 reports it to a service processor 25 once. Thereafter, the data processor stores system information, which is stored in the main storage device 20, in the system information area of the internal memory unit 11 by the microprogram control to recover the fault. Thus, system fault is prevented.

45. 发明专利

JPH03129525A INSTRUCTION PROCESSING SYSTEM FOR INFORMATION PROCESSOR 失效
公开(公告)号：JPH03129525A
公开(公告)日：1991-06-03
申请号：JP26863189
申请日：1989-10-16
申请人： HITACHI LTD
发明人： YAMAGATA MAKOTO , SHIMIZU NAOHIKO , SHIBATA MASABUMI
IPC分类号： G06F9/38
摘要： PURPOSE:To rapidly execute a branch instruction by preparing the 3rd instruction for specifying which is the 2nd instruction to be executed next to the 1st instruction and executing the 3rd instruction prior to the execution of the 1st instruction. CONSTITUTION:Two registers TAR0, TAR1 are prepared as target address registers(TARs) 5 observed from a program in order to hold branched addresses. A load target address(LTA) instruction and a branch target on condition(BTC) instruction are respectively prepared as an instruction for loading a branched address to the TARs 5 and an instruction for branching data to an address specified by the TARs 5. Since an individual instruction can execute pipeline processing without delaying it through the number of instructions is increased, the processing performance of the information processor is improved.

46. 发明专利

JPH02110614A DATA PROCESSOR 失效
公开(公告)号：JPH02110614A
公开(公告)日：1990-04-23
申请号：JP26149788
申请日：1988-10-19
申请人： HITACHI LTD
发明人： SHIBATA MASABUMI , YAMAGATA MAKOTO
IPC分类号： G06F1/08 , G06F1/10 , G06F1/12
摘要： PURPOSE:To make a data processor high in performance by providing a measuring means to measure the delay time of a logic circuit, and changing the operating system of the logic circuit when the delay time exceeds the range of some definite value. CONSTITUTION:A clock signal outputted from a clock signal generation circuit 1 is supplied to the logic circuit 5 through a clock signal line 6, and simultaneously, is inputted to a comparator 4. The delay time of the logic circuit 5 is measured by a ring oscillator 2, and the output of the ring oscillator 2 is connected to the input of another side of the comparator 4 through a frequency division circuit 3. Thus, the delay time of the logic circuit 5 and a clock signal period are compared in the comparator 4, and when the delay time is late, an operating system instruction signal 7 is outputted to the logic circuit 5. Thus, since the operating system optimum to the delay time of the logic circuit can be selected dynamically, the performance of the logic circuit can be improved.

47. 发明专利

JPH0279142A SYSTEM FOR PROCESSING KEY INFORMATION REWRITING INSTRUCTION 失效
公开(公告)号：JPH0279142A
公开(公告)日：1990-03-19
申请号：JP22998088
申请日：1988-09-16
申请人： HITACHI LTD
发明人： TAMANO AKIHIRO , MACHIDA MASAYUKI , YAMAMOTO AKIO , WATABE SHINYA , YAMAGATA MAKOTO
IPC分类号： G06F12/10 , G06F12/14
摘要： PURPOSE:To improve the processing efficiency of a key information rewriting instruction by comparing key information rewriting data which become the object to be rewritten with a main storage key in a main storage device, and when the data do not coincide with the key, executing a key buffer invalidating process. CONSTITUTION:In the case of executing a key information rewriting instruction for key performing a main storage key 62 rewriting process, the key information rewriting data which become the object to be rewritten are compared with the main storage key 62 in a main storage device 61, and when the data do not coincide with the key 62, a key buffer invalidating process is executed. In addition, the key information rewriting data which become the object to be rewritten are compared with the copy of the main storage key 62 in an instruction processor 51, and when the data do not coincide with the copy, the key buffer invalidating process is executed. Accordingly, execution of a partial purging process on a unnecessary address conversion buffer 53 is not performed. Therefore, the processing performance of a key information rewriting instruction can be improved.

48. 发明专利

JPS63269232A TIMER CONTROL SYSTEM FOR VIRTUAL COMPUTER SYSTEM 失效
公开(公告)号：JPS63269232A
公开(公告)日：1988-11-07
申请号：JP10413187
申请日：1987-04-27
申请人： HITACHI LTD
发明人： YAMAGATA MAKOTO
IPC分类号： G06F9/46 , G06F9/48
摘要： PURPOSE:To efficiently perform the timer interruption of a guest with addition of a relatively small amount of hardware by setting either of the timer value of the guest and that of a host, by which interruption first occurs, to an actual timer mechanism. CONSTITUTION:The timer interruption of the guest occurs when the interruption time comes after interrupt masks 14 and 15 for the guest are opened to set the timer value to an actual timer mechanism 6 or when a guest interruption pending register 5 is set, and the timer interruption of the host occurs when the interruption time comes after interruption masks 12 and 13 for the host are opened to set the timer value of the host to the actual timer mechanism 6. When the interruption time occurs after interruption masks 12 and 13 for the guest are closed and the timer value of the guest is set to the actual timer mechanism 6, the timer value of the host is set to the actual timer mechanism 6 by a microprogram and the interruption pending register 5 of the guest is set.

49. 发明专利

JPS62138948A DATA TRANSFERRING EQUIPMENT 失效
公开(公告)号：JPS62138948A
公开(公告)日：1987-06-22
申请号：JP27890485
申请日：1985-12-13
申请人： HITACHI LTD
发明人： OGAWA TETSUJI , SATO TADASHI , NINOMIYA KAZUHIKO , SHIBATA HIDEAKI , YAMAGATA MAKOTO
IPC分类号： G06F3/06 , G06F13/12
摘要： PURPOSE:To widen a data transfer width between a channel equipment and a common control part by distributing a data buffering control to respective channel equipments, executing independently the control and executing collectively the transfer control of data with a main memory device except it at a common control part. CONSTITUTION:Channel equipments 12-15 have respectively the common hardware constitution. A channel control device 11 to control channel equipments 12-15 to the time division is further connected to a main memory device 10 and executes the data transfer control at the section of the main memory device 10. Respective channel equipments 12-15 execute the data transfer control at the section of an I/O device connected and corresponded to the I/O device respectively and have a data buffer 30. Thus, the data transfer width between an I/O device 16 and a channel equipment 12 is about one byte, and on the other hand, the data width between the channel control device 11 and the channel equipment 12 is eight bytes. For such a reason, the data neck between the channel control device 11 and the channel equipment 12 is deleted.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式