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1. 发明专利

DE3931514A1 Communication control system - has multiple processors connects via channel controller connected to outputs 未知
公开(公告)号：DE3931514A1
公开(公告)日：1990-03-22
申请号：DE3931514
申请日：1989-09-21
申请人： HITACHI LTD
发明人： WASHIO KAZUTOSHI , KOYAMA TOSHIAKI , OGAWA TETSUJI
IPC分类号： G06F15/16 , G06F13/00 , G06F13/12 , G06F15/17 , G06F15/177
摘要： A number of host computers have CPU's (1) with associated communication control units (2) that connect iwth a common control system (3). The host computer channels connect with a channel adapter (4) operated by a service precessor (6). The adaptor has a number of communication processor modules (5) that provide output onto transmission lines. The channel adaptor has interface stages on the host computerr side and these connect with a selector that connects with output control interface units. Control of the internal cycle of the adapter is provided by a microprocessor based module. ADVANTAGE - Provides high speed communication between host computers and control processors.

2. 发明专利

DE3688759T2 未知
公开(公告)号：DE3688759T2
公开(公告)日：1994-01-05
申请号：DE3688759
申请日：1986-03-12
申请人： HITACHI LTD
发明人： OGAWA TETSUJI , KATO MASAO
IPC分类号： G06F13/12 , G06F13/26
摘要： An input/output control system includes an external data controller (23) connected to a plurality of input/output units (143), a central processor (21), and a main storage (20) accessible from the external data controller (23) and the central processor (21). The main storage (20) has a storage area (115) corresponding to each. input/output unit (143) and a storage area (116) storing information to configure a' queue for each class determining a start priority of each input/output unit (143). At execution of a start instruction, the central processor (21) sets a control information of the input/output unit (143) to an associated storage area (115) of the main storage (20) and updates the queue configure information. The external data controller (23) starts an input/output unit (143) registered to a queue having a higher priority. The start operation is achieved according to the control information of the input/output unit (143) stored in the main storage (20). 1

3. 发明专利

DE3931514C2 未知
公开(公告)号：DE3931514C2
公开(公告)日：1996-01-25
申请号：DE3931514
申请日：1989-09-21
申请人： HITACHI LTD
发明人： WASHIO KAZUTOSHI , KOYAMA TOSHIAKI , OGAWA TETSUJI
IPC分类号： G06F15/16 , G06F13/00 , G06F13/12 , G06F15/17 , G06F15/177 , G06F13/36 , G06F13/40

4. 发明专利

DE3688759D1 未知
公开(公告)号：DE3688759D1
公开(公告)日：1993-09-02
申请号：DE3688759
申请日：1986-03-12
申请人： HITACHI LTD
发明人： OGAWA TETSUJI , KATO MASAO
IPC分类号： G06F13/12 , G06F13/26
摘要： An input/output control system includes an external data controller (23) connected to a plurality of input/output units (143), a central processor (21), and a main storage (20) accessible from the external data controller (23) and the central processor (21). The main storage (20) has a storage area (115) corresponding to each. input/output unit (143) and a storage area (116) storing information to configure a' queue for each class determining a start priority of each input/output unit (143). At execution of a start instruction, the central processor (21) sets a control information of the input/output unit (143) to an associated storage area (115) of the main storage (20) and updates the queue configure information. The external data controller (23) starts an input/output unit (143) registered to a queue having a higher priority. The start operation is achieved according to the control information of the input/output unit (143) stored in the main storage (20). 1

5. 发明专利

JPH05204817A DATA TRANSFER EQUIPMENT 失效
公开(公告)号：JPH05204817A
公开(公告)日：1993-08-13
申请号：JP1281592
申请日：1992-01-28
申请人： HITACHI LTD
发明人： UENO HITOSHI , SATO TAKAO , OGAWA TETSUJI , KINOSHITA TOSHIYUKI , YOSHIOKA SEIICHIROU
IPC分类号： G06F12/08 , G06F13/10 , G06F13/12
摘要： PURPOSE:To secure maximum data throughput almost without decreasing program execution performance by preparing two small-capacity buffers for transfer in a hardware system area(HSA). CONSTITUTION:A read command 102 is executed by the microprogram control 128 in a channel device 116 and data transferred from an input/output device 18 are written in the A plane 113 of the buffer for data transfer of an extended storage device(ES); when the writing operation is ended, an ES data transfer circuit 122 is actuated and the data begin to be transferred from the buffer A plane 113 to ES 124. Then the channel device 116 writes following data transferred from the input/output device 118 in the B plane 14 of the ES data transfer buffer. The speed of ES data transfer from the input/output device 118 to the ES transfer buffer is slower than the speed of the data transfer from the ES transfer buffer to the ES124, so the channel device 116 transfers the data to the ES 124 at the end of the data writing to the B plane 114.

6. 发明专利

JPH03145605A OPTICAL FIBER CONNECTION SYSTEM 失效
公开(公告)号：JPH03145605A
公开(公告)日：1991-06-20
申请号：JP28296789
申请日：1989-11-01
申请人： HITACHI LTD
发明人： NINOMIYA KAZUHIKO , OGAWA TETSUJI
IPC分类号： G02B6/26
摘要： PURPOSE:To eliminate decrease in the quantity of light due to a difference in the core diameter of an external cable by specifying the core diameters of repeating cables in a device. CONSTITUTION:When the repeating fiber cables which connect the external optical fiber cable to a transmission and reception module for a light signal is provided, the core diameters of the input and output repeating cables are determined so that gamma i

7. 发明专利

JPH01150956A METHOD FOR TESTING CHANNEL DEVICE AND CHANNEL DEVICE THEREFOR 失效
公开(公告)号：JPH01150956A
公开(公告)日：1989-06-13
申请号：JP30854487
申请日：1987-12-08
申请人： HITACHI LTD
发明人： OGAWA TETSUJI , MORIKAWA TAKASHI
IPC分类号： G06F13/12 , G06F13/00
摘要： PURPOSE:To execute an enough test without using a special IOS (I/O simulator) equipment by mutually connecting channels in one computer system or mutually connecting the channels between the two computer systems and operating one of a pair of the channels to be mutually connected as the IOS. CONSTITUTION:For this channel testing method, the other channel is used as the IOS for test. Namely, in order to test a first channel 20, an output terminal group for input and output device and an input terminal group are respectively connected to the input terminal group and output terminal group for the input and output device of a second channel 21 and the second channel 21 is caused to simulate the signal response and generating operation of the input and output device. Thus, without using the special IOS device, the operation test of the channel can be enough executed and accordingly, the test or diagnosis of the channel can be executed economically and efficiently.

8. 发明专利

JPS6368953A INPUT/OUTPUT DEVICE ADDRESSING SYSTEM 失效
公开(公告)号：JPS6368953A
公开(公告)日：1988-03-28
申请号：JP21160886
申请日：1986-09-10
申请人： HITACHI LTD
发明人： MORIKAWA TAKASHI , OGAWA TETSUJI , SASAKI AKIO , SATO KIICHI
IPC分类号： G06F13/12 , G06F13/14
摘要： PURPOSE:To allocate a different address at every control unit by containing a difference value of a unit address of every channel bus, in logical input/output control information. CONSTITUTION:In control information of a logical control unit 6, numbers of the maximum 8 pieces of input/output channels to which the control unit concerned is connected, and a difference value of a control unit address on the respective input/output channels are contained. Accordingly, at the time of executing an access to input/output devices 5a, 5b, 5c... from an input/output control device 4a or 4b, the input/output device addresses are different in accordance with the units 4a, 4b. As for the control unit address difference values corresponding to the respective channels, 00, 20, 00 and 20 are set in accordance with CHID0, CHID1, CHID2 and CHID3, respectively. These pieces of information are supplied to a hardware as I/O constituting information at the time of constructing a system.

9. 发明专利

JPS62180443A INITIALIZATION SYSTEM FOR COMPUTER SYSTEM 失效
公开(公告)号：JPS62180443A
公开(公告)日：1987-08-07
申请号：JP2183486
申请日：1986-02-03
申请人： HITACHI LTD
发明人： MORIKAWA TAKASHI , OGAWA TETSUJI
IPC分类号： G06F1/00 , G06F9/06 , G06F13/00
摘要： PURPOSE:To shorten the time needed for a series of sequences in a power-on mode by reducing the time needed for initialization of hardware. CONSTITUTION:The IOCDS 5a of a DF 5 is transferred to the HSA 1a of an MS1 via an input/output interface line instead of a scan path. In this case, the IOCDS 5a read out of the DF 5 is transferred to a general area 1b in the MS1 and then to the HSA 1a. In such a way, the transfer speed of the input/ output interface line reaches up to a range between several 10KB/sec and several MB/sec. Thus the transfer time is reduced down to the order of several seconds.

10. 发明专利

JPS61223959A CHANNEL PATH SELECTING SYSTEM 失效
公开(公告)号：JPS61223959A
公开(公告)日：1986-10-04
申请号：JP6357285
申请日：1985-03-29
申请人： HITACHI LTD
发明人： OGAWA TETSUJI
IPC分类号： G06F13/12
摘要： PURPOSE:To improve the processing efficiency of a system by selecting one of usable channel paths among plural channel paths when an I/O is started. CONSTITUTION:When an I/O start instruction is issued from a central processing unit 11, a channel path selecting device 122 of the channel system 12 read a control word of a sub channel to conduct a test whether or not a path fixed bit in a flag byte is set. When the bit is set, a path is fixed and an I/O is started. When not set, an optional channel is selected to start the I/O. When a selected channel path is in use, and when the path is fixed, the operation is reserved until the use is released and when optional, other channel is selected for restart. When the I/O start is successful, a reserve command bringing the level of a path fixed bit to 1 and a release command bringing the level of path fixed bit to 0 are tested.

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