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41. 发明授权

US07382168B2 Buffer circuit with multiple voltage range 失效
标题翻译：具有多电压范围的缓冲电路
公开(公告)号：US07382168B2
公开(公告)日：2008-06-03
申请号：US11215663
申请日：2005-08-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H03B1/00
CPC分类号： H03K19/018585 , H03K19/018521 , H03K19/018592
摘要： A buffer circuit operative at multiple power supply voltage levels includes first and second buffers, the first buffer being configured for operation with a first voltage source and the second buffer being operative with a second voltage source. The buffer circuit further includes a controllable isolation circuit. An output of the first buffer connects to an external pad of the buffer circuit, and an output of the second buffer connects to the pad via the isolation circuit. The buffer circuit is selectively operative in at least a first mode or a second mode in response to at least a first control signal. The isolation circuit is operative in the first mode to substantially isolate the second buffer from the external pad and is operative in the second mode to connect the output of the second buffer to the external pad.
摘要翻译：在多个电源电压电平下工作的缓冲电路包括第一和第二缓冲器，第一缓冲器被配置为与第一电压源一起操作，第二缓冲器与第二电压源一起工作。缓冲电路还包括可控隔离电路。第一缓冲器的输出连接到缓冲电路的外部焊盘，第二缓冲器的输出经由隔离电路连接到焊盘。响应于至少第一控制信号，缓冲电路在至少第一模式或第二模式中选择性地工作。隔离电路在第一模式下工作，以将第二缓冲器与外部焊盘基本隔离，并且在第二模式下工作，以将第二缓冲器的输出连接到外部焊盘。

42. 发明申请

US20080074814A1 Circuit for Selectively Bypassing a Capacitive Element 有权
标题翻译：选择性绕过电容元件的电路
公开(公告)号：US20080074814A1
公开(公告)日：2008-03-27
申请号：US11535719
申请日：2006-09-27
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H02H9/00
CPC分类号： H03K17/063
摘要： A circuit for selectively bypassing a capacitive element includes at least one NMOS device selectively connectable across the capacitive element to be bypassed, and at least first and second PMOS devices. The PMOS devices are selectively connectable together in series across the capacitive element to be bypassed. The NMOS device provides a first bypass path and the first and second PMOS devices collectively provide a second bypass path.
摘要翻译：用于选择性地绕过电容元件的电路包括至少一个可选择地连接在待旁路的电容元件上的NMOS器件，以及至少第一和第二PMOS器件。 PMOS器件可选择性地连接在电容元件上串联在一起以被旁路。 NMOS器件提供第一旁路路径，并且第一和第二PMOS器件共同提供第二旁路路径。

43. 发明授权

US08536925B2 Voltage level translator circuit 有权
标题翻译：电压电平转换电路
公开(公告)号：US08536925B2
公开(公告)日：2013-09-17
申请号：US12598352
申请日：2008-12-29
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Jeffrey J. Nagy , Peter J. Nicholas
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Jeffrey J. Nagy , Peter J. Nicholas
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H03K3/0375
摘要： A voltage translator circuit (320) includes an input stage (322) adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch (326) adapted for connection to a second voltage supply (VDD33) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp (324) coupled between the input stage (322) and the latch (326). The voltage clamp (322) is operative to set a maximum voltage across the latch (326) to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit (320) generates a first output signal (II) at a junction between the latch (326) and the voltage clamp (324). The voltage translator circuit generates a second output signal (15) at a junction between the voltage clamp (324) and the input stage (322).
摘要翻译：电压转换器电路（320）包括适于接收参考第一电压源（VDD核心）的输入信号的输入级（322），适于连接到第二电压源（VDD33）的锁存器（326）至少临时存储输入信号的逻辑状态，以及耦合在输入级（322）和锁存器（326）之间的电压钳位（324）。电压钳（322）用于将锁存器（326）两端的最大电压设定为第一规定电平，并将输入级两端的最大电压设定为第二规定电平。电压转换器电路（320）在闩锁（326）和电压钳（324）之间的连接处产生第一输出信号（II）。电压转换器电路在电压钳位器（324）和输入级（322）之间的接点处产生第二输出信号（15）。

44. 发明授权

US07529071B2 Circuit for selectively bypassing a capacitive element 有权
标题翻译：有选择地绕过电容元件的电路
公开(公告)号：US07529071B2
公开(公告)日：2009-05-05
申请号：US11535719
申请日：2006-09-27
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H02H3/22
CPC分类号： H03K17/063
摘要： A circuit for selectively bypassing a capacitive element includes at least one NMOS device selectively connectable across the capacitive element to be bypassed, and at least first and second PMOS devices. The PMOS devices are selectively connectable together in series across the capacitive element to be bypassed. The NMOS device provides a first bypass path and the first and second PMOS devices collectively provide a second bypass path.
摘要翻译：用于选择性地绕过电容元件的电路包括至少一个可选择地连接在待旁路的电容元件上的NMOS器件，以及至少第一和第二PMOS器件。 PMOS器件可选择性地连接在电容元件上串联在一起以被旁路。 NMOS器件提供第一旁路路径，并且第一和第二PMOS器件共同提供第二旁路路径。

45. 发明授权

US07498860B2 Buffer circuit having multiplexed voltage level translation 有权
标题翻译：具有多路电压电平转换的缓冲电路
公开(公告)号：US07498860B2
公开(公告)日：2009-03-03
申请号：US11691590
申请日：2007-03-27
申请人： Dipankar Bhattacharya , Carol A. Huber , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Carol A. Huber , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H03L5/00
CPC分类号： H03K19/017581 , H03K19/01759
摘要： A buffer circuit is selectively operative in one of at least a first mode and a second mode as a function of a first control signal supplied to the buffer circuit. The buffer circuit includes interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage level. The output signal is a function of the second control signal in the first mode and is a function of the third control signal in the second mode. The buffer circuit further includes at least first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including at least one control input operative to receive the output signal generated by the interface circuitry.
摘要翻译：作为提供给缓冲电路的第一控制信号的函数，缓冲器电路有选择地以至少第一模式和第二模式中的至少一个工作。缓冲电路包括接口电路，其操作以接收参考第一电压电平的至少第二和第三控制信号，并产生参考第二电压电平的输出信号，第二电压电平大于第一电压电平。输出信号是第一模式中的第二控制信号的函数，并且是第二模式中的第三控制信号的函数。缓冲电路还包括耦合到接口电路的至少第一和第二电路部分，第一和第二电路部分中的每一个包括至少一个控制输入，其操作以接收由接口电路产生的输出信号。

46. 发明申请

US20090002017A1 Multiple-Mode Compensated Buffer Circuit 有权
标题翻译：多模式补偿缓冲电路
公开(公告)号：US20090002017A1
公开(公告)日：2009-01-01
申请号：US11768496
申请日：2007-06-26
申请人： Dipankar Bhattacharya , Gregg R. Harleman , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Gregg R. Harleman , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H03K19/0175 , H03K19/02
CPC分类号： H03K19/00376
摘要： A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected. The respective control signals supplied to the predrivers collectively represent a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode.
摘要翻译：以至少第一模式和第二模式之一工作的补偿缓冲器电路包括多个输出块和多个预驱动器，每个预驱动器具有连接到相应一个输出块的输入的输出。输出块的各输出端连接在一起形成缓冲电路的输出。输出块按顺序排列并且被二进制加权，使得给定的一个输出块的驱动强度大约是在给定输出块之前的输出块的驱动强度的两倍。每个预驱动器根据提供给预驱动器的控制信号选择性地使连接到其上的相应输出块能够补偿用于缓冲电路可能经受的PVT变化的缓冲电路。提供给预驱动器的各个控制信号共同表示二进制码字，第二模式中的二进制码字等价于第一模式中的二进制码字的算术移位。

47. 发明申请

US20080297226A1 Enhanced Output Impedance Compensation 有权
标题翻译：增强输出阻抗补偿
公开(公告)号：US20080297226A1
公开(公告)日：2008-12-04
申请号：US11755955
申请日：2007-05-31
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Antonio M. Marques , Bernard L. Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Antonio M. Marques , Bernard L. Morris
IPC分类号： G06G7/12
CPC分类号： H03K19/00384 , H04L5/16 , H04L25/0264
摘要： A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal. The processor is operative to control the value of the second current so that the second current is substantially equal to the first current.
摘要翻译：用于补偿至少第一MOS器件的输出阻抗的补偿电路，其中PVT变化对其可能经受的PVT变化包括：第一电流源，其产生具有基本恒定值的第一电流和产生第一MOS器件的第二电流源第二电流具有可被编程为呈现给第二电流源的至少一个控制信号的函数的值。比较器连接到第一和第二电流源的相应输出，并且可操作以测量第一和第二电流的相应值之间的差，并产生指示第一电流和第二电流的相对幅度的输出信号。连接在比较器和第二电流源之间的反馈装置中的处理器接收比较器产生的输出信号，并产生用于根据输出信号控制第二电流的控制信号。处理器可操作以控制第二电流的值，使得第二电流基本上等于第一电流。

48. 发明授权

US07391825B2 Comparator circuit having reduced pulse width distortion 失效
标题翻译：比较器电路具有减小的脉冲宽度失真
公开(公告)号：US07391825B2
公开(公告)日：2008-06-24
申请号：US11046995
申请日：2005-01-31
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H04B10/06
CPC分类号： H03K5/2481 , H03K5/12
摘要： A comparator circuit having reduced pulse width distortion includes a differential amplifier operative to receive at least first and second signals and to amplify a difference between the first and second signals. The differential amplifier generates a difference signal at an output thereof which is a function of the difference between the first and second signals. An output stage is included in the comparator circuit for receiving the difference signal and for generating an output signal of the comparator circuit, the output signal being representative of the difference signal, the output stage having a switching point associated therewith. The comparator circuit further includes a voltage source coupled to the output of the differential amplifier. The voltage source is operative to generate a reference signal for establishing a common-mode voltage of the difference signal generated by the differential amplifier. The reference signal is substantially centered about the switching point of the output stage and substantially tracks the switching point over variations in process, voltage and/or temperature conditions to which the comparator circuit is subjected.
摘要翻译：具有减小的脉冲宽度失真的比较器电路包括差分放大器，其操作以接收至少第一和第二信号并且放大第一和第二信号之间的差。差分放大器在其输出处产生差分信号，其作为第一和第二信号之间的差异的函数。输出级包括在比较器电路中，用于接收差分信号并产生比较器电路的输出信号，该输出信号代表差分信号，输出级具有与之相关的切换点。比较器电路还包括耦合到差分放大器的输出的电压源。电压源用于产生用于建立由差分放大器产生的差分信号的共模电压的参考信号。参考信号基本上以输出级的切换点为中心，并且基本上跟踪比较器电路所经受的过程，电压和/或温度条件变化的切换点。

49. 发明授权

US07057545B1 Semiconductor resistance compensation with enhanced efficiency 失效
标题翻译：半导体电阻补偿效率提高
公开(公告)号：US07057545B1
公开(公告)日：2006-06-06
申请号：US11170127
申请日：2005-06-29
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H03M1/12
CPC分类号： H01L28/20 , H01L27/0802
摘要： A semiconductor resistor circuit having a controllable resistance associated therewith includes a plurality of resistor segments connected in a series and/or parallel configuration. The resistor circuit further includes a plurality of switches controlling connection of respective ones of the resistor segments to the resistor circuit, to thereby selectively control a resistance of the resistor circuit in response to respective control signals presented to the switches. The resistor circuit is selectively controllable in discrete resistance intervals, the resistance intervals being unequal to one another. The resistor segments have resistance values that are selected such that a percentage resistance variation across each of the respective resistance intervals as a function of process, voltage and/or temperature conditions to which the resistor circuit is subjected is substantially the same.
摘要翻译：具有与其相关联的可控电阻的半导体电阻器电路包括以串联和/或并联配置连接的多个电阻器段。电阻电路还包括多个开关，其控制各个电阻器段与电阻器电路的连接，从而响应于提供给开关的相应控制信号选择性地控制电阻器电路的电阻。电阻电路可以以离散的电阻间隔选择性地控制，电阻间隔彼此不相等。电阻器段具有电阻值，其被选择为使得作为电阻器电路经受的过程，电压和/或温度条件的函数的各个电阻间隔中的每个电阻变化的百分比电阻变化基本相同。

50. 发明申请

US20060203405A1 Power pin to power pin electro-static discharge (ESD) clamp 有权
公开(公告)号：US20060203405A1
公开(公告)日：2006-09-14
申请号：US11076850
申请日：2005-03-11
申请人： Dipankar Bhattacharya , John Kriz , Che Leung , Duane Loeper , Yehuda Smooha
发明人： Dipankar Bhattacharya , John Kriz , Che Leung , Duane Loeper , Yehuda Smooha
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： An ESD clamp circuit for use between separate power rails. An ESD clamp is based on a wide nMOSFET. A symmetrical circuit is designed vis-à-vis the two power rails, with respect to ground, allowing discharge of an ESD surge in both polarities of stress. An nMOSFET device drives the gate of a large nMOSFET (e.g., having a device width between 1000 and 10,000 microns). The large power rail-to-power rail nMOSFET has its gate controlled by the output inverter stage of either ESD detection circuit connected to a respective power supply rail. The gate is switched to a common ground during normal operation of the integrated circuit.

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