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41. 发明申请

US20110320696A1 EDRAM REFRESH IN A HIGH PERFORMANCE CACHE ARCHITECTURE 有权
标题翻译： EDRAM在高性能缓存架构中刷新
公开(公告)号：US20110320696A1
公开(公告)日：2011-12-29
申请号：US12822245
申请日：2010-06-24
申请人： Michael Fee , Arthur J. O'Neill, JR. , Robert J. Sonnelitter, III
发明人： Michael Fee , Arthur J. O'Neill, JR. , Robert J. Sonnelitter, III
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0893 , G06F13/14 , G06F13/16 , G06F13/1605 , G06F13/1636 , G11C11/406 , G11C11/40603 , G11C11/40618 , G11C2207/104
摘要： A memory refresh requestor, a memory request interpreter, a cache memory, and a cache controller on a single chip. The cache controller configured to receive a memory access request, the memory access request for a memory address range in the cache memory, detect that the cache memory located at the memory address range is available, and send the memory access request to the memory request interpreter when the memory address range is available. The memory request interpreter configured to receive the memory access request from the cache controller, determine if the memory access request is a request to refresh a contents of the memory address range, and refresh data in the memory address range when the memory access request is a request to refresh memory.
摘要翻译：在单个芯片上的存储器刷新请求器，存储器请求解释器，高速缓存存储器和高速缓存控制器。缓存控制器被配置为接收存储器访问请求，对高速缓冲存储器中的存储器地址范围的存储器访问请求，检测位于存储器地址范围的高速缓存存储器可用，并将存储器访问请求发送到存储器请求解释器当存储器地址范围可用时。存储器请求解释器被配置为从高速缓存控制器接收存储器访问请求，确定存储器访问请求是否是刷新存储器地址范围的内容的请求，以及当存储器访问请求是存储器访问请求时刷新存储器地址范围中的数据请求刷新内存。

42. 发明申请

US20110314183A1 SYSTEM AND METHOD FOR MANAGING DATAFLOW IN A TEMPORARY MEMORY 失效
标题翻译：用于管理临时存储器中的数据流的系统和方法
公开(公告)号：US20110314183A1
公开(公告)日：2011-12-22
申请号：US12820589
申请日：2010-06-22
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F3/00 , G06F5/14
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/073 , G06F12/0897 , Y02D10/13
摘要： A method of managing a temporary memory includes: receiving a request to transfer data from a source location to a destination location, the data transfer request associated with an operation to be performed, the operation selected from an input into an intermediate temporary memory and an output; checking a two-state indicator associated with the temporary memory, the two-state indicator having a first state indicating that an immediately preceding operation on the temporary memory was an input to the temporary memory and a second state indicating that the immediately preceding operation was an output from the temporary memory; and performing the operation responsive to one of: the operation being an input operation and the two-state indicator being in the second state, indicating that the immediately preceding operation was an output; and the operation being an output operation and the two-state indicator being in the first state, indicating that the immediately preceding operation was an input.
摘要翻译：管理临时存储器的方法包括：接收从源位置传送数据到目的地位置的请求，与要执行的操作相关联的数据传输请求，从输入中选择的中间临时存储器和输出 ; 检查与临时存储器相关联的两状态指示符，两状态指示符具有指示临时存储器上的紧接在前的操作是临时存储器的输入的第一状态，以及指示紧接在前的操作是第二状态的第二状态从临时存储器输出; 并且响应于以下操作中的一个执行操作：作为输入操作的操作和处于第二状态的两状态指示器，指示紧接在前的操作是输出; 操作是输出操作，两状态指示灯处于第一状态，表示紧接在前的操作是输入。

43. 发明授权

US06516393B1 Dynamic serialization of memory access in a multi-processor system 失效
标题翻译：在多处理器系统中的存储器访问的动态序列化
公开(公告)号：US06516393B1
公开(公告)日：2003-02-04
申请号：US09676185
申请日：2000-09-29
申请人： Michael Fee , Pak-kin Mak
发明人： Michael Fee , Pak-kin Mak
IPC分类号： G06F1200
CPC分类号： G06F12/084 , G06F12/0828 , G06F13/1663
摘要： A method for resolving address contention and prioritization of access to resources within a shared memory system includes dynamically creating ordered lists of requests for each contested resource. A new request is added to the lists only after a conflict is recognized. Since the resource conflict does not always exist, there is no impact to a request for an uncontested resources.
摘要翻译：一种用于解决在共享存储器系统内访问资源的地址竞争和优先级排列的方法包括动态地创建每个有争议的资源的请求的有序列表。只有在确认冲突之后，才会将新请求添加到列表中。由于资源冲突并不总是存在，因此对无争议资源的请求没有任何影响。

44. 发明授权

US08560767B2 Optimizing EDRAM refresh rates in a high performance cache architecture 失效
标题翻译：在高性能缓存架构中优化EDRAM刷新率
公开(公告)号：US08560767B2
公开(公告)日：2013-10-15
申请号：US13546687
申请日：2012-07-11
申请人： Timothy C. Bronson , Michael Fee , Arthur J. O'Neill, Jr. , Scott B. Swaney
发明人： Timothy C. Bronson , Michael Fee , Arthur J. O'Neill, Jr. , Scott B. Swaney
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0855
摘要： Embodiments relate to embedded Dynamic Random Access Memory (eDRAM) refresh rates in a high performance cache architecture. An aspect includes receiving a plurality of first signals. A refresh request is transmitted via a refresh requestor to a cache memory at a first refresh rate which includes an interval, including a subset of the first signals. The first refresh rate corresponds to a maximum refresh rate. A refresh counter is reset based on receiving a second signal. The refresh counter is incremented after receiving each of a number of refresh requests. A current count is transmitted from a refresh counter to the refresh requestor based on receiving a third signal. The refresh request is transmitted at a second refresh rate, which is less than the first refresh rate. The refresh request is transmitted based on receiving the current count from the refresh counter and determining that the current count is greater than a refresh threshold.
摘要翻译：实施例涉及高性能高速缓存架构中的嵌入式动态随机存取存储器（eDRAM）刷新率。一个方面包括接收多个第一信号。经由刷新请求者的刷新请求以包括包括第一信号的子集的间隔的第一刷新率被发送到高速缓冲存储器。第一个刷新率对应于最大刷新率。基于接收到第二信号，刷新计数器被复位。刷新计数器在接收到多个刷新请求之后递增。基于接收到第三信号，从刷新计数器向刷新请求者发送当前计数。刷新请求以小于第一刷新率的第二刷新率发送。基于从刷新计数器接收当前计数并确定当前计数大于刷新阈值来发送刷新请求。

45. 发明授权

US08495452B2 Handling corrupted background data in an out of order execution environment 失效
标题翻译：在乱序执行环境中处理损坏的背景数据
公开(公告)号：US08495452B2
公开(公告)日：2013-07-23
申请号：US13024775
申请日：2011-02-10
申请人： Michael Fee , Christian Habermann , Christian Jacobi , Diana L. Orf , Martin Recktenwald , Hans-Werner Tast , Ralf Winkelmann
发明人： Michael Fee , Christian Habermann , Christian Jacobi , Diana L. Orf , Martin Recktenwald , Hans-Werner Tast , Ralf Winkelmann
IPC分类号： H03M13/00
CPC分类号： G06F11/1064
摘要： Handling corrupted background data in an out of order processing environment. Modified data is stored on a byte of a word having at least one byte of background data. A byte valid vector and a byte store bit are added to the word. Parity checking is done on the word. If the word does not contain corrupted background date, the word is propagated to the next level of cache. If the word contains corrupted background data, a copy of the word is fetched from a next level of cache that is ECC protected, the byte having the modified data is extracted from the word and swapped for the corresponding byte in the word copy. The word copy is then written into the next level of cache that is ECC protected.
摘要翻译：在乱序处理环境中处理损坏的背景数据。修改的数据存储在具有至少一个字节的背景数据的字的字节上。一个字节有效向量和一个字节存储位被加到该字中。对这个词进行奇偶校验。如果该单词不包含损坏的背景日期，该单词将传播到下一级缓存。如果该单词包含已损坏的背景数据，则该字的副本将从ECC保护的高级缓存中提取，具有修改后的数据的字节将从该字中提取出来并交换为字副本中的相应字节。然后将该字复制到被保护的ECC缓存的下一级。

46. 发明授权

US08495287B2 Clock-based debugging for embedded dynamic random access memory element in a processor core 失效
标题翻译：基于时钟的调试，用于处理器内核中的嵌入式动态随机存取存储器元件
公开(公告)号：US08495287B2
公开(公告)日：2013-07-23
申请号：US12822882
申请日：2010-06-24
申请人： Adam B. Collura , Michael Fee , Arthur J. O'Neill, Jr. , Gerard M. Salem , Robert J. Sonnelitter, III
发明人： Adam B. Collura , Michael Fee , Arthur J. O'Neill, Jr. , Gerard M. Salem , Robert J. Sonnelitter, III
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F11/073 , G06F11/0751
摘要： A method of debugging an embedded dynamic random access memory (eDRAM) element of a processor core is provided. An aspect includes, based on an error occurring in the eDRAM element, stopping a functional clock, and not stopping a refresh clock. Another aspect includes, based on the functional clock being stopped, creating a fence signal that prevents all commands other than a refresh command, the refresh command being based on the refresh clock, from entering into the eDRAM element. Another aspect includes initializing a line fetch controller of the processor core with at least one of write data and read data. Another aspect includes restarting the functional clock. Another aspect includes performing at least one of write requests and read requests to the eDRAM element based on the at least one of the write data and the read data from the line fetch controller based on the functional clock.
摘要翻译：提供了一种调试处理器核心的嵌入式动态随机存取存储器（eDRAM）元件的方法。一个方面包括基于eDRAM元件中发生的错误，停止功能时钟，而不是停止刷新时钟。另一方面包括基于停止的功能时钟，创建围栏信号，该屏障信号防止刷新命令以外的所有命令（刷新命令基于刷新时钟）进入eDRAM元素。另一方面包括用写入数据和读取数据中的至少一个初始化处理器核心的线取指控制器。另一方面包括重启功能时钟。另一方面包括基于功能时钟，基于来自线取指控制器的写入数据和读取数据中的至少一个，向eDRAM元件执行至少一个写入请求和读取请求。

47. 发明授权

US08468421B2 Memory system for error checking fetch and store data 失效
标题翻译：用于错误检查和存储数据的内存系统
公开(公告)号：US08468421B2
公开(公告)日：2013-06-18
申请号：US12821917
申请日：2010-06-23
申请人： Michael Fee , Arthur J. O'Neill, Jr.
发明人： Michael Fee , Arthur J. O'Neill, Jr.
IPC分类号： G11C29/00
CPC分类号： G06F11/1064
摘要： A memory system is provided. The memory system includes a memory element that is configured to selectively output data stored to and data fetched from the memory element. An error checking station is configured to receive the data stored to and the data fetched from the memory element. The error checking station is further configured to perform error checking on the data.
摘要翻译：提供了一种存储系统。存储器系统包括存储元件，其被配置为选择性地输出存储到存储元件中的数据和从存储器元件取出的数据。错误检查站被配置为接收存储的数据和从存储器元件获取的数据。错误检查站还被配置为对数据执行错误检查。

48. 发明授权

US08327078B2 Dynamic trailing edge latency absorption for fetch data forwarded from a shared data/control interface 失效
标题翻译：从共享数据/控制接口转发的抓取数据的动态后沿延迟吸收
公开(公告)号：US08327078B2
公开(公告)日：2012-12-04
申请号：US12822884
申请日：2010-06-24
申请人： Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Robert J. Sonnelitter, III
发明人： Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Robert J. Sonnelitter, III
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0897 , G06F2212/1024
摘要： A computer-implemented method for managing data transfer in a multi-level memory hierarchy that includes receiving a fetch request for allocation of data in a higher level memory, determining whether a data bus between the higher level memory and a lower level memory is available, bypassing an intervening memory between the higher level memory and the lower level memory when it is determined that the data bus is available, and transferring the requested data directly from the higher level memory to the lower level memory.
摘要翻译：一种用于管理多级存储器层级中的数据传输的计算机实现的方法，包括：接收用于在较高级存储器中分配数据的提取请求，确定所述较高级存储器和较低级存储器之间的数据总线是否可用，当确定数据总线可用时，绕过高级存储器和较低级存储器之间的中间存储器，并将所请求的数据直接从较高级存储器传送到下级存储器。

49. 发明授权

US08327070B2 Method for optimizing sequential data fetches in a computer system 失效
标题翻译：用于优化计算机系统中的顺序数据提取的方法
公开(公告)号：US08327070B2
公开(公告)日：2012-12-04
申请号：US12822486
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Michael Fee , Arthur J. O'Neill, Jr.
发明人： Ekaterina M. Ambroladze , Michael Fee , Arthur J. O'Neill, Jr.
IPC分类号： G06F12/00
CPC分类号： G06F12/1408 , G06F12/0802
摘要： A computer implemented method of optimizing sequential data fetches in a computer system is provided. The method includes fetching a data segment from a main memory, the data segment having a plurality of target data entries; extracting a first portion of the data segment and storing the first portion into a target data cache, the first portion having a first target data entry; and storing the data segment into an intermediate cache line buffer in communication with the target data cache to enable subsequent fetches to a number of target data entries in the data segment.
摘要翻译：提供了一种在计算机系统中优化顺序数据提取的计算机实现的方法。该方法包括从主存储器获取数据段，该数据段具有多个目标数据条目; 提取所述数据段的第一部分并将所述第一部分存储到目标数据高速缓存中，所述第一部分具有第一目标数据条目; 以及将数据段存储到与目标数据高速缓存进行通信的中间高速缓存行缓冲器中，以便能够随后提取数据段中的多个目标数据条目。

50. 发明申请

US20110320863A1 DYNAMIC RE-ALLOCATION OF CACHE BUFFER SLOTS 审中-公开
标题翻译：缓存缓冲区的动态重新分配
公开(公告)号：US20110320863A1
公开(公告)日：2011-12-29
申请号：US12822407
申请日：2010-06-24
申请人： Ekaterina M. Amroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Amroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F11/20 , G06F12/08 , G06F11/00
CPC分类号： G06F12/126 , G06F11/0724 , G06F11/073 , G06F11/0793 , G06F11/1666 , G06F11/20 , G06F12/0802 , G06F2212/1032
摘要： Dynamic re-allocation of cache buffer slots includes moving data out of a reserved buffer slot upon detecting an error in the reserved buffer slot, creating a new buffer slot, and storing the data moved out of the reserved buffer slot in the new buffer slot.
摘要翻译：高速缓冲存储器时隙的动态重新分配包括在检测到保留的缓冲器时隙中的错误时产生保留的缓冲器时隙中的数据，创建新的缓冲时隙，以及将保留的缓冲时隙中移出的数据存储在新的缓冲时隙中。

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