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41. 发明授权

US07335565B2 Metal-oxide-semiconductor device having improved performance and reliability 有权
标题翻译：具有提高的性能和可靠性的金属氧化物半导体器件
公开(公告)号：US07335565B2
公开(公告)日：2008-02-26
申请号：US11348597
申请日：2006-02-07
申请人： Muhammed Ayman Shibib , Shuming Xu
发明人： Muhammed Ayman Shibib , Shuming Xu
IPC分类号： H01L21/336
CPC分类号： H01L29/0634 , H01L29/1083 , H01L29/402 , H01L29/407 , H01L29/4175 , H01L29/7816 , H01L29/7835
摘要： A method for forming a MOS device includes the steps of forming a gate proximate an upper surface of a semiconductor layer, the semiconductor layer including a substrate of a first conductivity type and a second layer of a second conductivity type; forming first and second source/drain regions of the second conductivity type in the second layer proximate the upper surface of the second layer, the first source/drain region being spaced laterally from the second source/drain region, the gate being formed at least partially between the first and second source/drain regions; and forming at least one electrically conductive trench in the second layer between the gate and the second source/drain region, the trench being formed proximate the upper surface of the semiconductor layer and extending substantially vertically through the second layer to the substrate. The step of forming the trench includes the steps of forming an insulating layer substantially lining sidewalls of the trench, and substantially filling the trench with an electrically conductive material.
摘要翻译：一种用于形成MOS器件的方法包括以下步骤：在半导体层的上表面附近形成栅极，所述半导体层包括第一导电类型的衬底和第二导电类型的第二层; 在靠近第二层的上表面的第二层中形成第二导电类型的第一和第二源极/漏极区域，第一源极/漏极区域与第二源极/漏极区域横向间隔开，栅极至少部分地形成在第一和第二源/漏区之间; 以及在所述栅极和所述第二源极/漏极区域之间的所述第二层中形成至少一个导电沟槽，所述沟槽形成在所述半导体层的所述上表面附近并且基本上垂直延伸穿过所述第二层到所述衬底。形成沟槽的步骤包括以下步骤：形成基本上衬有沟槽侧壁的绝缘层，并用导电材料基本上填充沟槽。

42. 发明授权

US07279744B2 Control of hot carrier injection in a metal-oxide semiconductor device 有权
标题翻译：在金属氧化物半导体器件中控制热载流子注入
公开(公告)号：US07279744B2
公开(公告)日：2007-10-09
申请号：US10977732
申请日：2004-10-29
申请人： Peter L. Gammel , Isik C. Kizilyalli , Marco G. Mastrapasqua , Muhammed Ayman Shibib , Zhijian Xie , Shuming Xu
发明人： Peter L. Gammel , Isik C. Kizilyalli , Marco G. Mastrapasqua , Muhammed Ayman Shibib , Zhijian Xie , Shuming Xu
IPC分类号： H01L29/76
CPC分类号： H01L29/402 , H01L29/41 , H01L29/7835
摘要： An MOS device is formed including a semiconductor layer of a first conductivity type, and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A drift region is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer and above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the first and second source/drain regions. The MOS device further includes a shielding structure formed on the insulating layer above at least a portion of the drift region. The shielding structure is configured such that an amount of hot carrier injection degradation in the MOS device is controlled as a function of an amount of coverage of the shielding structure over an upper surface of the drift region.
摘要翻译：形成MOS器件，其包括第一导电类型的半导体层，以及形成在靠近半导体层的上表面的半导体层中的第二导电类型的第一和第二源极/漏极区域，第一和第二源极/漏极区域相对于彼此间隔开。在靠近半导体层的上表面的半导体层中至少部分地在第一和第二源/漏区之间形成漂移区。绝缘层形成在半导体层的上表面的至少一部分上方和漂移区的至少一部分上方。栅极形成在绝缘层上并且至少部分地在第一和第二源/漏区之间。 MOS器件还包括形成在漂移区的至少一部分上方的绝缘层上的屏蔽结构。屏蔽结构被配置为使得MOS器件中的热载流子注入劣化量被控制为在漂移区域的上表面上的屏蔽结构的覆盖量的函数。

43. 发明申请

US20070007593A1 METAL-OXIDE-SEMICONDUCTOR DEVICE WITH ENHANCED SOURCE ELECTRODE 审中-公开
标题翻译：具有增强源电极的金属氧化物半导体器件
公开(公告)号：US20070007593A1
公开(公告)日：2007-01-11
申请号：US11532250
申请日：2006-09-15
申请人： Frank Baiocchi , Bailey Jones , Muhammed Shibib , Shuming Xu
发明人： Frank Baiocchi , Bailey Jones , Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/402 , H01L29/4175 , H01L29/456
摘要： An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.
摘要翻译：形成MOS器件，其包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的第一源极/漏极区域和形成在半导体层中的第二导电类型的第二源极/漏极区域，以及与第一源极/漏极区间隔开。栅极形成在半导体层的上表面附近并且至少部分地形成在第一和第二源/漏区之间。所述MOS器件还包括至少一个触点，所述至少一个触点包括在所述第一源极/漏极区域的至少一部分上形成并且与所述第一源极/漏极区域的至少一部分电连接的硅化物层，所述硅化物层从所述栅极横向延伸。触点还包括直接形成在硅化物层上的至少一个绝缘层。

44. 发明授权

US07087959B2 Metal-oxide-semiconductor device having an enhanced shielding structure 有权
标题翻译：具有增强的屏蔽结构的金属氧化物半导体器件
公开(公告)号：US07087959B2
公开(公告)日：2006-08-08
申请号：US10920656
申请日：2004-08-18
申请人： Muhammed Ayman Shibib , Shuming Xu
发明人： Muhammed Ayman Shibib , Shuming Xu
IPC分类号： H01L29/94
CPC分类号： H01L29/4175 , H01L29/407 , H01L29/66704 , H01L29/7816 , H01L29/7825 , H01L29/7835
摘要： An MOS device includes a semiconductor layer formed on a substrate, the substrate defining a horizontal plane and a vertical direction normal to the horizontal plane. First and second source/drain regions are formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A gate is formed proximate the upper surface of the semiconductor layer and disposed at least partially between the first and second source/drain regions. A first dielectric region is formed in the MOS device, the first dielectric region defining a trench extending downward from the upper surface of the semiconductor layer to a first distance into the semiconductor layer, the first dielectric region being formed between the first and second source/drain regions. The MOS device further includes a shielding structure formed primarily in the first dielectric region, at least a portion of the shielding structure being disposed adjacent a bottom wall of the first dielectric region and/or one or more sidewalls of the first dielectric region.
摘要翻译： MOS器件包括形成在衬底上的半导体层，衬底限定水平面和垂直于水平面的垂直方向。第一和第二源极/漏极区域形成在靠近半导体层的上表面的半导体层中，第一和第二源极/漏极区域相对于彼此间隔开。栅极形成在半导体层的上表面附近并且至少部分地设置在第一和第二源/漏区之间。在MOS器件中形成第一电介质区域，第一电介质区域限定从半导体层的上表面向下延伸到半导体层的第一距离的沟槽，第一介电区域形成在第一和第二源极/ 漏区。 MOS器件还包括主要形成在第一电介质区域中的屏蔽结构，屏蔽结构的至少一部分邻近第一电介质区域的底壁和/或第一介电区域的一个或多个侧壁设置。

45. 发明申请

US20060071283A1 Thick oxide region in a semiconductor device and method of forming same 失效
标题翻译：半导体器件中的厚氧化物区域及其形成方法
公开(公告)号：US20060071283A1
公开(公告)日：2006-04-06
申请号：US10953750
申请日：2004-09-29
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/76
CPC分类号： H01L21/76208
摘要： A method of forming an oxide region in a semiconductor device includes the steps of forming a plurality of trenches in a semiconductor layer of the device, the trenches being formed in close relative proximity to one another, and oxidizing the semiconductor layer such that an insulating layer is formed on at least sidewalls and bottom walls of the trenches. The trenches are configured such that the insulating layer formed as a result of the oxidizing step substantially fills the trenches and substantially consumes the semiconductor layer between corresponding pairs of adjacent trenches. In this manner, a substantially continuous oxide region is formed throughout the plurality of trenches.
摘要翻译：在半导体器件中形成氧化物区域的方法包括以下步骤：在器件的半导体层中形成多个沟槽，沟槽彼此相对靠近地形成，并且氧化半导体层，使得绝缘层形成在沟槽的至少侧壁和底壁上。沟槽被配置成使得由氧化步骤的结果形成的绝缘层基本上填充沟槽并且基本上消耗相应的相邻的沟槽对之间的半导体层。以这种方式，在整个多个沟槽中形成基本上连续的氧化物区域。

46. 发明授权

US07005703B2 Metal-oxide-semiconductor device having improved performance and reliability 有权
标题翻译：具有提高的性能和可靠性的金属氧化物半导体器件
公开(公告)号：US07005703B2
公开(公告)日：2006-02-28
申请号：US10688231
申请日：2003-10-17
申请人： Muhammed Ayman Shibib , Shuming Xu
发明人： Muhammed Ayman Shibib , Shuming Xu
IPC分类号： H01L29/94
CPC分类号： H01L29/0634 , H01L29/1083 , H01L29/402 , H01L29/407 , H01L29/4175 , H01L29/7816 , H01L29/7835
摘要： An MOS device includes a semiconductor layer comprising a substrate of a first conductivity type and a second layer of a second conductivity type formed on at least a portion of the substrate. First and second source/drain regions of the second conductivity type are formed in the second layer proximate an upper surface of the second layer, the second layer being spaced laterally from the first source/drain region. A gate is formed above the second layer proximate the upper surface of the second layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one electrically conductive trench formed in the second layer between the gate and the second source/drain region, the trench being formed proximate the upper surface of the semiconductor layer and extending substantially vertically through the second layer to the substrate. The MOS device exhibits reduced HCI effects and/or improved high-frequency performance.
摘要翻译： MOS器件包括半导体层，该半导体层包括形成在衬底的至少一部分上的第一导电类型的衬底和第二导电类型的第二层。第二导电类型的第一和第二源极/漏极区域在靠近第二层的上表面的第二层中形成，第二层与第一源极/漏极区域横向隔开。栅极形成在靠近第二层的上表面的第二层上方，并且至少部分地在第一和第二源/漏区之间。 MOS器件还包括形成在栅极和第二源极/漏极区域之间的第二层中的至少一个导电沟槽，沟槽在半导体层的上表面附近形成并且基本上垂直延伸穿过第二层到衬底。 MOS器件表现出降低的HCI效应和/或改善的高频性能。

47. 发明申请

US20060038224A1 Metal-oxide-semiconductor device having an enhanced shielding structure 有权
公开(公告)号：US20060038224A1
公开(公告)日：2006-02-23
申请号：US10920656
申请日：2004-08-18
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/76
CPC分类号： H01L29/4175 , H01L29/407 , H01L29/66704 , H01L29/7816 , H01L29/7825 , H01L29/7835
摘要： An MOS device includes a semiconductor layer formed on a substrate, the substrate defining a horizontal plane and a vertical direction normal to the horizontal plane. First and second source/drain regions are formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A gate is formed proximate the upper surface of the semiconductor layer and disposed at least partially between the first and second source/drain regions. A first dielectric region is formed in the MOS device, the first dielectric region defining a trench extending downward from the upper surface of the semiconductor layer to a first distance into the semiconductor layer, the first dielectric region being formed between the first and second source/drain regions. The MOS device further includes a shielding structure formed primarily in the first dielectric region, at least a portion of the shielding structure being disposed adjacent a bottom wall of the first dielectric region and/or one or more sidewalls of the first dielectric region.

48. 发明授权

US06890804B1 Metal-oxide-semiconductor device formed in silicon-on-insulator 有权
标题翻译：形成在绝缘体上硅的金属氧化物半导体器件
公开(公告)号：US06890804B1
公开(公告)日：2005-05-10
申请号：US10719195
申请日：2003-11-21
申请人： Muhammed Ayman Shibib , Shuming Xu
发明人： Muhammed Ayman Shibib , Shuming Xu
IPC分类号： H01L21/336 , H01L21/84 , H01L29/417 , H01L29/76 , H01L29/78 , H01L29/786
CPC分类号： H01L29/78609 , H01L29/402 , H01L29/41741 , H01L29/66772 , H01L29/7835 , H01L29/78624 , H01L29/78645
摘要： A semiconductor device includes a substrate of a first conductivity type, an insulating layer formed on at least a portion of the substrate, and an epitaxial layer of a second conductivity type formed on at least a portion of the insulating layer. First and second source/drain regions of the second conductivity type are formed in the epitaxial layer proximate an upper surface of the epitaxial layer, the first and second source/drain regions being spaced laterally from one another. A gate is formed above the epitaxial layer proximate the upper surface of the epitaxial layer and at least partially between the first and second source/drain regions. The device further includes a first source/drain contact formed through the epitaxial layer and insulating layer, the first source/drain contact configured so as to be in direct electrical connection with the substrate, the first source/drain region and the epitaxial layer, and a second source/drain contact formed through the epitaxial layer, the second source/drain contact configured so as to be in direct electrical connection with the second source/drain region.
摘要翻译：半导体器件包括第一导电类型的衬底，形成在衬底的至少一部分上的绝缘层和形成在绝缘层的至少一部分上的第二导电类型的外延层。第二导电类型的第一和第二源极/漏极区域在接近外延层的上表面的外延层中形成，第一和第二源极/漏极区域彼此横向间隔开。栅极形成在邻近外延层的上表面的外延层的上方，并且至少部分地在第一和第二源/漏区之间。该器件还包括通过外延层和绝缘层形成的第一源极/漏极接触点，第一源极/漏极接触构造成与衬底，第一源极/漏极区域和外延层直接电连接，以及通过所述外延层形成的第二源极/漏极接触，所述第二源极/漏极接触构造成与所述第二源极/漏极区域直接电连接。

49. 发明授权

US06423987B1 Self-protect thyristor 失效
标题翻译：自保晶闸管
公开(公告)号：US06423987B1
公开(公告)日：2002-07-23
申请号：US09424367
申请日：2000-04-19
申请人： Rainer Constapel , Heinrich Sciilangenotto , Shuming Xu
发明人： Rainer Constapel , Heinrich Sciilangenotto , Shuming Xu
IPC分类号： H01L2974
CPC分类号： H01L29/7455 , H01L29/7436 , H01L29/749
摘要： With a self-protect thyristor, having a MOSFET (M1) that is connected in series with the thyristor and a second, self-controlled MOSFET (M2) between the p-base of the thyristor and the external cathode (KA), several unit cells for the thyristor are arranged parallel connected in a semiconductor wafer. The voltage at the series MOSFET (M1) functions as an indicator for the overcurrent and excess temperature, and an additional MOSFET (M4) is provided where source (region) is connected conducting to the source of the series MOSFET (M1), where drain is conductivity connected with the gate of the series MOSFET (M1) and where gate conductivity connected with the drain of the series MOSFET (M1). A resistance (Rg) is provided between the gate electrode (G1) of the series MOSFET (M1) and the gate (G) of the thyristor.
摘要翻译：具有自保护晶闸管，具有与晶闸管串联连接的MOSFET（M1）和晶闸管的p基极与外部阴极（KA）之间的第二个自控MOSFET（M2），多个单元用于晶闸管的单元被并联连接在半导体晶片中。串联MOSFET（M1）的电压用作过电流和过温的指示器，并且提供一个额外的MOSFET（M4），其中源极（区域）连接到串联MOSFET（M1）的源极，其中漏极是与串联MOSFET（M1）的栅极连接的导电性，栅极电导率与串联MOSFET（M1）的漏极连接。在串联MOSFET（M1）的栅电极（G1）和晶闸管的栅极（G）之间提供电阻（Rg）。

50. 发明授权

US11107914B2 Metal-oxide semiconductor for field-effect transistor having enhanced high-frequency performance 有权
公开(公告)号：US11107914B2
公开(公告)日：2021-08-31
申请号：US16774498
申请日：2020-01-28
申请人： Shuming Xu
发明人： Shuming Xu
IPC分类号： H01L29/78 , H01L29/66 , H01L29/51 , H01L29/423 , H01L29/40 , H01L29/10 , H01L29/08 , H01L29/06 , H01L21/265 , H01L21/762
摘要： An LDMOS device includes a doped drift region of a first conductivity type formed on an upper surface of a substrate having a second conductivity type. A body region of the second conductivity type is formed proximate an upper surface of the doped drift region. Source and drain regions of the first conductivity type are formed proximate an upper surface of the body region and doped drift region, respectively, and spaced laterally from one another. A gate is formed over the body region and between the source and drain regions. The gate is formed on a first insulating layer for electrically isolating the gate from the body region. A shielding structure is formed over at least a portion of the doped drift region on a second insulating layer. The gate and shielding structure are spaced laterally from one another to thereby reduce parasitic gate-to-drain capacitance.

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