专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US08180931B2 USB-attached-SCSI flash-memory system with additional command, status, and control pipes to a smart-storage switch 失效
标题翻译： USB连接的SCSI闪存系统，带有智能存储交换机的附加命令，状态和控制管道
公开(公告)号：US08180931B2
公开(公告)日：2012-05-15
申请号：US12651334
申请日：2009-12-31
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F3/0661 , G06F3/0613 , G06F3/0688 , G11C11/5678 , G11C13/0004 , G11C16/102 , G11C2216/30
摘要： An electronic flash-memory card has additional pipes for commands and status messages so that data pipes are not clogged with commands and status messages, allowing for a higher data throughput. The command and status pipes are activated when a UAS/BOT detector detects that a host is using a USB-Attached-SCSI (UAS) mode rather than a Bulk-Only-Transfer (BOT) mode. The host can send additional commands and data without waiting for completion of a prior command when operating in UAS mode but not while operating in BOT mode. A command queue (CQ) in the device re-orders commands for accessing flash memory and merges data in a RAM buffer. Smaller 1 KB USB packets in the data pipes are merged into larger 8 KB payloads in the RAM buffer, allowing for more efficient flash access.
摘要翻译：电子闪存卡具有用于命令和状态消息的附加管道，使得数据管道不被命令和状态消息阻塞，从而允许更高的数据吞吐量。当UAS / BOT检测器检测到主机正在使用USB-Attached-SCSI（UAS）模式而不是Bulk-Only-Transfer（BOT）模式时，命令和状态管道将被激活。主机可以发送附加的命令和数据，而不必在UAS模式下操作时等待先前的命令完成，而不能在BOT模式下运行。设备中的命令队列（CQ）重新命令用于访问闪存的命令，并将数据合并到RAM缓冲区中。数据管道中较小的1 KB USB数据包被合并到RAM缓冲区中的较大的8 KB有效载荷中，从而实现更高效的闪存访问。

42. 发明申请

US20120040477A1 AI EPOXY ADJUSTMENT 审中-公开
标题翻译： AI环氧调节
公开(公告)号：US20120040477A1
公开(公告)日：2012-02-16
申请号：US12856180
申请日：2010-08-13
申请人： Frank Yu , Eric Hsieh , Ares Twu , W. L. Hsu
发明人： Frank Yu , Eric Hsieh , Ares Twu , W. L. Hsu
IPC分类号： H01L21/66 , B05C5/00
CPC分类号： H01L22/20 , H01L22/12 , H01L24/743 , H01L2224/83192
摘要： A method and apparatus for dispensing a volume of die attach adhesive onto a surface can include an optical system which images the dispensed volume of die attach adhesive. A two-dimensional area covered by the die attach adhesive and a die attach dispense pressure can be used as a comparison with a reference value to determine whether the volume of die attach adhesive dispensed is sufficient. The reference value can take into account viscosity changes of the die attach adhesive, so that the volume of die attach adhesive dispensed during production can be determined. The volume dispensed can be automatically adjusted in situ during production using a computer system.
摘要翻译：用于将体积的管芯附着粘合剂分配到表面上的方法和设备可以包括对分配的管芯附着粘合剂体积进行成像的光学系统。可以使用由芯片附着粘合剂覆盖的二维区域和管芯附着分配压力作为与参考值的比较，以确定分配的管芯附着粘合剂的体积是否足够。参考值可以考虑管芯附着粘合剂的粘度变化，从而可以确定在生产期间分配的管芯附着粘合剂的体积。在使用计算机系统的生产期间，分配的体积可以在现场自动调整。

43. 发明授权

US08112574B2 Swappable sets of partial-mapping tables in a flash-memory system with a command queue for combining flash writes 有权
标题翻译：具有用于组合闪存写入的命令队列的闪存系统中的可转换的部分映射表
公开(公告)号：US08112574B2
公开(公告)日：2012-02-07
申请号：US12347306
申请日：2008-12-31
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7203 , G11C16/102 , G11C2216/30
摘要： A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N−1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables.
摘要翻译：闪存控制器具有访问多电平单元（MLC）闪存的物理块的闪存接口。扩展通用串行总线（EUSB）接口将主机命令加载到命令队列中，其中写入被重新排序并组合以减少闪存写入。 RAM中的部分逻辑到物理L2P映射表仅具有N组L2P映射表中的1个的条目。其他N-1组存储在闪存中，并在发生L2P表错误时被提取到RAM中。映射所需的RAM大大降低。数据缓冲器存储一页主机写入数据。扇区写入使用数据缓冲区进行合并。当写入不同的页面时，数据缓冲区被刷新闪存，而当L2P表错过发生时，部分逻辑到物理映射表被刷新为闪存，当主机地址是N组的L2P中的不同的一个映射表。

44. 发明申请

US20090240873A1 Multi-Level Striping and Truncation Channel-Equalization for Flash-Memory System 有权
标题翻译：闪存系统的多级条带和截断信道均衡
公开(公告)号：US20090240873A1
公开(公告)日：2009-09-24
申请号：US12475457
申请日：2009-05-29
申请人： Frank Yu , Charles C. Lee , Abraham C. Ma , Myeongjin Shin
发明人： Frank Yu , Charles C. Lee , Abraham C. Ma , Myeongjin Shin
IPC分类号： G06F12/00 , G06F12/02 , H03M13/00
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/0631 , G06F3/0688 , G06F2212/7203 , G06F2212/7208 , G11C11/5678 , G11C13/0004 , G11C29/765
摘要： Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers.
摘要翻译：截断将所有闪存通道的可用条带数据容量减小到最小闪存通道的容量。固态磁盘（SSD）具有智能存储交换机，通过截断来保护从条带数据容量中移除的闪存存储。超出条带数据容量的额外存储被访问为不带条纹的分散数据。随着更多的坏块出现，条带数据容量的大小随着时间的推移而减少。一级条形图存储所有闪存通道的条纹和分散容量，并映射散射和条纹数据。每个闪存通道都具有一个非易失性存储器件（NVMD），该器件具有将逻辑块地址（LBA）转换为访问NVMD中闪存的物理块地址（PBA）的低级别控制器。磨损平整和坏块重映射由每个NVMD进行。源和阴影闪存块由NVMD回收。两级智能存储交换机支持三级控制器。

45. 发明申请

US20090113121A1 Swappable Sets of Partial-Mapping Tables in a Flash-Memory System With A Command Queue for Combining Flash Writes 有权
标题翻译：具有用于组合Flash写入的命令队列的闪存系统中可部署的部分映射表集
公开(公告)号：US20090113121A1
公开(公告)日：2009-04-30
申请号：US12347306
申请日：2008-12-31
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7203 , G11C16/102 , G11C2216/30
摘要： A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N−1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables.
摘要翻译：闪存控制器具有访问多电平单元（MLC）闪存的物理块的闪存接口。扩展通用串行总线（EUSB）接口将主机命令加载到命令队列中，其中写入被重新排序并组合以减少闪存写入。 RAM中的部分逻辑到物理L2P映射表仅具有N组L2P映射表中的1个的条目。其他N-1组存储在闪存中，并在发生L2P表错误时被提取到RAM中。映射所需的RAM大大降低。数据缓冲器存储一页主机写入数据。扇区写入使用数据缓冲区进行合并。当写入不同的页面时，数据缓冲区被刷新闪存，而当L2P表错过发生时，部分逻辑到物理映射表被刷新为闪存，当主机地址是N组的L2P中的不同的一个映射表。

46. 发明申请

US20080266991A1 Synchronous Page-Mode Phase-Change Memory with ECC and RAM Cache 失效
标题翻译：具有ECC和RAM缓存的同步页模式相变存储器
公开(公告)号：US20080266991A1
公开(公告)日：2008-10-30
申请号：US11769324
申请日：2007-06-27
申请人： Charles C. Lee , Frank Yu , David Q. Chow
发明人： Charles C. Lee , Frank Yu , David Q. Chow
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1044 , G11C7/1072 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0085 , G11C2213/79
摘要： Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.
摘要翻译：相变存储器（PCM）单元使用高电阻非晶和低电阻晶体状态的合金电阻存储数据。存储单元的设定电流脉冲的时间可以是100 ns，比读取或复位时间长得多。因此，写入时间取决于写入数据并且相对较长。页面模式缓存PCM设备具有高速缓存写入数据的查找表（LUT），该数据稍后被写入PCM存储体阵列。主机数据被锁存到行FIFO中并写入LUT中，从而将写入延迟减少到相对较慢的PCM。主机读取数据可由LUT提供或从PCM存储区中提取。 PCM组和LUT之间的多行页面缓冲区允许使用LUT进行更大的块传输。对LUT中的数据执行纠错码（ECC）检查和生成，将ECC数据写入PCM存储体中隐藏ECC延迟。

47. 发明授权

US08959280B2 Super-endurance solid-state drive with endurance translation layer (ETL) and diversion of temp files for reduced flash wear 有权
标题翻译：超耐力固态驱动器，具有耐力翻译层（ETL）和转移临时文件以减少闪光磨损
公开(公告)号：US08959280B2
公开(公告)日：2015-02-17
申请号：US13540569
申请日：2012-07-02
申请人： Frank Yu , Abraham C. Ma , Shimon Chen
发明人： Frank Yu , Abraham C. Ma , Shimon Chen
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/02 , G06F3/06 , G06F12/08 , G11C14/00 , G11C11/56 , G11C13/00 , G11C29/00
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/0631 , G06F3/0688 , G06F12/0868 , G06F2212/401 , G06F2212/7203 , G06F2212/7208 , G11C11/5678 , G11C13/0004 , G11C14/0018 , G11C29/765
摘要： A flash drive has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table that stores the data-type bits and pointers to data or tables in DRAM. Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.
摘要翻译：闪存驱动器通过减少对闪存的写入来提高耐用性和使用寿命。耐久性翻译层（ETL）在DRAM缓冲区中创建，并提供临时存储以减少闪存磨损。智能存储交换机（SSS）控制器将主机访问分类为内存管理，临时文件，文件分配表（FAT）和文件描述符块（FDB）条目所使用的页面文件以及用户数据文件时，分配数据类型位，使用地址从FAT读取的范围和文件扩展名。分页文件和临时文件不会写入闪存。部分页面数据由通过统一映射表指向的子扇区映射表进行打包和扇区映射，统一映射表将数据类型位和指针存储到DRAM中的数据或表。部分行业包装在一起，以减少DRAM的使用和闪存磨损。 DRAM中的备用/交换区域可减少闪存磨损。当纠错失败时，调整参考电压。

48. 发明授权

US08341332B2 Multi-level controller with smart storage transfer manager for interleaving multiple single-chip flash memory devices 有权
标题翻译：具有智能存储传输管理器的多电平控制器，用于交错多个单芯片闪存设备
公开(公告)号：US08341332B2
公开(公告)日：2012-12-25
申请号：US12186471
申请日：2008-08-05
申请人： Abraham C. Ma , David Q. Chow , Charles C. Lee , Frank Yu
发明人： Abraham C. Ma , David Q. Chow , Charles C. Lee , Frank Yu
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F3/0613 , G06F3/0616 , G06F3/064 , G06F3/0658 , G06F3/0664 , G06F3/0688 , G06F2212/7201 , G06F2212/7208 , G06F2212/7211 , G11C13/0004
摘要： A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device.
摘要翻译：固态磁盘（SSD）具有智能存储交换机，智能存储交易管理器重新命令用于访问下游单芯片闪存设备的主机命令。每个单芯片闪存设备具有将逻辑块地址（LBA）转换为访问单芯片闪存设备中的闪存块的物理块地址（PBA）的较低级别的控制器。磨损均衡和坏块重映射由每个单芯片闪存设备执行，并且在智能存储交换机中的虚拟存储处理器处于更高级别。智能存储事务管理器和单芯片闪存设备之间的虚拟存储网桥将LBA总线上的LBA交易桥接到单芯片闪存设备。单芯片闪速存储器件的多个通道之间的数据条带化和交错由智能存储事务管理器控制在高电平，而可以在每个单芯片闪速存储器件内执行进一步的交错和重新映射。

49. 发明授权

US08304871B2 Exposed die package for direct surface mounting 有权
标题翻译：暴露的裸片封装，用于直接表面安装
公开(公告)号：US08304871B2
公开(公告)日：2012-11-06
申请号：US13080320
申请日：2011-04-05
申请人： Frank Yu , Lance Wright , Chien-Te Feng , Sandra Horton
发明人： Frank Yu , Lance Wright , Chien-Te Feng , Sandra Horton
IPC分类号： H01L23/495
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/49541 , H01L24/29 , H01L24/48 , H01L24/73 , H01L2224/2919 , H01L2224/30181 , H01L2224/30505 , H01L2224/30519 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/73265 , H01L2924/00014 , H01L2924/01019 , H01L2924/1305 , H01L2924/1461 , H01L2924/181 , H01L2924/18165 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A packaged semiconductor device includes a semiconductor die including a substrate having a topside including active circuitry and a bottomside with at least one backside metal layer directly attached. A package including a molding material having a die pad and a plurality of leads is encapsulated within the molding material, wherein the leads include an exposed portion that includes a bonding portion. The topside of the semiconductor die is attached to the die pad, and the package includes a gap that exposes the backside metal layer along a bottom surface of the package. Bond wires couple pads on the topside of the semiconductor die to the leads. The bonding portions, the molding material along the bottom surface of the package, and the backside metal layer are all substantially planar to one another.
摘要翻译：封装的半导体器件包括半导体管芯，该半导体管芯包括具有包括有源电路的顶面的基板和具有直接附接的至少一个背侧金属层的底部底部。包括具有管芯焊盘和多个引线的成型材料的封装被封装在模制材料内，其中引线包括包括结合部分的暴露部分。半导体管芯的顶侧附接到管芯焊盘，并且封装件包括沿着封装的底表面暴露背面金属层的间隙。键合线将半导体芯片顶端的引线耦合到引线。接合部分，沿着封装的底表面的成型材料和背面金属层彼此基本上是平面的。

50. 发明授权

US08296467B2 Single-chip flash device with boot code transfer capability 有权
标题翻译：具有启动代码传输功能的单芯片闪存设备
公开(公告)号：US08296467B2
公开(公告)日：2012-10-23
申请号：US12947211
申请日：2010-11-16
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma , Shimon Chen
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma , Shimon Chen
IPC分类号： G06F3/00 , G06F12/00
CPC分类号： G06F9/4401 , G06F13/387 , G06F2213/3854
摘要： A Multi-Media Card (MMC) Single-Chip Flash Device (SCFD) contains a MMC flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM. Boot code and control code are selectively overwritten during a code updating operation to eliminate stocking issues.
摘要翻译：多媒体卡（MMC）单片闪存器件（SCFD）包含一个MMC闪存单片机和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。初始引导加载程序由状态机从闪存的第一页读取并写入小RAM。微控制器中的中央处理单元（CPU）从小型RAM读取指令，执行初始启动加载程序，从Flash读取更多的页面。这些页面被小RAM缓冲并写入较大的DRAM。一旦将扩展引导顺序写入DRAM，CPU将切换一个RAM_BASE位，以使DRAM从DRAM获取指令。然后从DRAM执行扩展启动顺序，将OS映像从闪存复制到DRAM。引导代码和控制代码在代码更新操作期间被有选择地覆盖以消除存货问题。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式