会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • Single-Chip Flash Device with Boot Code Transfer Capability
    • 具有启动代码传输能力的单芯片闪存设备
    • US20110066837A1
    • 2011-03-17
    • US12947211
    • 2010-11-16
    • Charles C. LeeAbraham C. MaFrank YuShimon Chen
    • Charles C. LeeAbraham C. MaFrank YuShimon Chen
    • G06F15/177G06F12/02G06F13/28G06F9/24
    • G06F9/4401G06F13/387G06F2213/3854
    • A Multi-Media Card (MMC) Single-Chip Flash Device (SCFD) contains a MMC flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM. Boot code and control code are selectively overwritten during a code updating operation to eliminate stocking issues.
    • 多媒体卡(MMC)单片闪存器件(SCFD)包含一个MMC闪存单片机和闪存大容量存储块,其中包含可寻址的闪存阵列,而不是随机寻址。 初始引导加载程序由状态机从闪存的第一页读取并写入小RAM。 微控制器中的中央处理单元(CPU)从小型RAM读取指令,执行初始启动加载程序,从Flash读取更多的页面。 这些页面被小RAM缓冲并写入较大的DRAM。 一旦将扩展引导顺序写入DRAM,CPU将切换一个RAM_BASE位,以使DRAM从DRAM获取指令。 然后从DRAM执行扩展启动顺序,将OS映像从闪存复制到DRAM。 引导代码和控制代码在代码更新操作期间被有选择地覆盖以消除存货问题。
    • 3. 发明授权
    • Single-chip flash device with boot code transfer capability
    • 具有启动代码传输功能的单芯片闪存设备
    • US08296467B2
    • 2012-10-23
    • US12947211
    • 2010-11-16
    • Charles C. LeeFrank YuAbraham C. MaShimon Chen
    • Charles C. LeeFrank YuAbraham C. MaShimon Chen
    • G06F3/00G06F12/00
    • G06F9/4401G06F13/387G06F2213/3854
    • A Multi-Media Card (MMC) Single-Chip Flash Device (SCFD) contains a MMC flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM. Boot code and control code are selectively overwritten during a code updating operation to eliminate stocking issues.
    • 多媒体卡(MMC)单片闪存器件(SCFD)包含一个MMC闪存单片机和闪存大容量存储块,其中包含可寻址的闪存阵列,而不是随机寻址。 初始引导加载程序由状态机从闪存的第一页读取并写入小RAM。 微控制器中的中央处理单元(CPU)从小型RAM读取指令,执行初始启动加载程序,从Flash读取更多的页面。 这些页面被小RAM缓冲并写入较大的DRAM。 一旦将扩展引导顺序写入DRAM,CPU将切换一个RAM_BASE位,以使DRAM从DRAM获取指令。 然后从DRAM执行扩展启动顺序,将OS映像从闪存复制到DRAM。 引导代码和控制代码在代码更新操作期间被有选择地覆盖以消除存货问题。
    • 4. 发明授权
    • Low-power USB superspeed device with 8-bit payload and 9-bit frame NRZI encoding for replacing 8/10-bit encoding
    • 低功耗USB超速设备,具有8位有效负载和9位帧NRZI编码,用于替换8/10位编码
    • US08166221B2
    • 2012-04-24
    • US12831160
    • 2010-07-06
    • Charles C. LeeFrank YuAbraham C. MaJim Chin-Nan NiShimon Chen
    • Charles C. LeeFrank YuAbraham C. MaJim Chin-Nan NiShimon Chen
    • G06F13/12G06F13/00
    • G06F13/385G11C16/102G11C2216/30Y02D10/14Y02D10/151
    • A Low-power flash-memory device uses a modified Universal-Serial-Bus (USB) 3.0 Protocol to reduce power consumption. The bit clock is slowed to reduce power and the need for pre-emphasis when USB cable lengths are short in applications. Data efficiency is improved by eliminating the 8/10-bit encoder and instead encoding sync and framing bytes as 9-bit symbols. Data bytes are expanded by bit stuffing only when a series of six ones occurs in the data. Header and payload data is transmitted as nearly 8-bits per data byte while framing is 9-bits per symbol, much less than the standard 10 bits per byte. Low-power link layers, physical layers, and scaled-down protocol layers are used. A card reader converter hub allows USB hosts to access low-power USB devices. Only one flash device is accessed, reducing power compared with standard USB broadcasting to multiple devices.
    • 低功耗闪存设备使用修改后的通用串行总线(USB)3.0协议来降低功耗。 当应用程序中的USB电缆长度短时,位时钟减慢了功率,并且需要预加重。 通过消除8/10位编码器并将同步和成帧字节编码为9位符号来提高数据效率。 数据字节只有在数据中出现一系列6个数据字节时才能通过位填充进行扩展。 标头和有效载荷数据以每个数据字节近8位的形式传输,而成帧是每个符号9位,远远小于每个字节的标准10位。 使用低功率链路层,物理层和缩小协议层。 读卡器转换器集线器允许USB主机访问低功耗USB设备。 只有一个闪存设备被访问,与标准的USB广播相比,将功耗降低到多个设备。
    • 7. 发明授权
    • Method and systems for storing and accessing data in USB attached-SCSI (UAS) and bulk-only-transfer (BOT) based flash-memory device
    • 用于在USB连接SCSI(UAS)和仅批量传输(BOT)的闪存设备中存储和访问数据的方法和系统
    • US08060670B2
    • 2011-11-15
    • US12717918
    • 2010-03-04
    • I-Kang YuCharles C. LeeShimon ChenAbraham C. Ma
    • I-Kang YuCharles C. LeeShimon ChenAbraham C. Ma
    • G06F12/02G06F13/36G06F3/00
    • G06F13/1684G11C16/102G11C2216/30
    • Methods and systems for storing and accessing data in UAS based flash memory device are disclosed. UAS based flash memory device comprises a controller and a plurality of non-volatile memories (e.g., flash memory) it controls. Controller is configured for connecting to a UAS host via a physical layer (e.g., plug and wire based on USB 3.0) and for conducting data transfer operations via two sets of logical pipes. Controller further comprises a random-access-memory (RAM) buffer configured for enabling parallel and duplex data transfer operations through the sets of logical pipes. In addition, a Smart Storage Switch configured for connecting multiple non-volatile memory devices is included in the controller. Finally, a security module/engine/unit is provided for data security via user authentication data encryption/decryption of the device. Furthermore, the flash memory device includes an optical transceiver configured for optical connection to a host also configured with an optical transceiver.
    • 公开了在基于UAS的闪存设备中存储和访问数据的方法和系统。 基于UAS的闪存设备包括控制器和它控制的多个非易失性存储器(例如闪存)。 控制器被配置为经由物理层(例如,基于USB 3.0的插头和线路)连接到UAS主机,并且用于经由两组逻辑管道进行数据传输操作。 控制器还包括随机存取存储器(RAM)缓冲器,其配置用于通过逻辑管道集合实现并行和双工数据传输操作。 此外,控制器中还包括配置用于连接多个非易失性存储设备的智能存储交换机。 最后,通过设备的用户认证数据加密/解密来提供用于数据安全的安全模块/引擎/单元。 此外,闪速存储器件包括被配置用于光学连接到也配置有光收发器的主机的光收发器。
    • 8. 发明申请
    • METHODS AND SYSTEMS FOR STORING AND ACCESSING DATA IN UAS BASED FLASH-MEMORY DEVICE
    • 用于存储和访问基于UAS的闪速存储器件中的数据的方法和系统
    • US20100185808A1
    • 2010-07-22
    • US12717918
    • 2010-03-04
    • I-Kang YuCharles C. LeeShimon ChenAbraham C. Ma
    • I-Kang YuCharles C. LeeShimon ChenAbraham C. Ma
    • G06F12/02G06F13/36G06F12/14G06F13/00
    • G06F13/1684G11C16/102G11C2216/30
    • Methods and systems for storing and accessing data in UAS based flash memory device are disclosed. UAS based flash memory device comprises a controller and a plurality of non-volatile memories (e.g., flash memory) it controls. Controller is configured for connecting to a UAS host via a physical layer (e.g., plug and wire based on USB 3.0) and for conducting data transfer operations via two sets of logical pipes. Controller further comprises a random-access-memory (RAM) buffer configured for enabling parallel and duplex data transfer operations through the sets of logical pipes. In addition, a Smart Storage Switch configured for connecting multiple non-volatile memory devices is included in the controller. Finally, a security module/engine/unit is provided for data security via user authentication data encryption/decryption of the device. Furthermore, the flash memory device includes an optical transceiver configured for optical connection to a host also configured with an optical transceiver.
    • 公开了在基于UAS的闪存设备中存储和访问数据的方法和系统。 基于UAS的闪存设备包括控制器和它控制的多个非易失性存储器(例如闪存)。 控制器被配置为经由物理层(例如,基于USB 3.0的插头和线路)连接到UAS主机,并且用于经由两组逻辑管道进行数据传输操作。 控制器还包括随机存取存储器(RAM)缓冲器,其配置用于通过逻辑管道集合实现并行和双工数据传输操作。 此外,控制器中还包括配置用于连接多个非易失性存储设备的智能存储交换机。 最后,通过设备的用户认证数据加密/解密来提供用于数据安全的安全模块/引擎/单元。 此外,闪速存储器件包括被配置用于光学连接到也配置有光收发器的主机的光收发器。
    • 10. 发明授权
    • Flash-memory device with RAID-type controller
    • 具有RAID型控制器的闪存设备
    • US08543742B2
    • 2013-09-24
    • US13494409
    • 2012-06-12
    • Frank YuAbraham C. MaShimon Chen
    • Frank YuAbraham C. MaShimon Chen
    • G06F13/28G06F3/00G06F11/00
    • G06F13/28G06F3/0604G06F3/0658G06F3/0688G06F11/1064G06F12/0246G06F12/0607G06F13/385G06F2212/7208G06F2212/7211G06F2213/3802
    • A smart flash drive has one or more levels of smart storage switches and a lower level of single-chip flash devices (SCFD's). A SCFD contains flash memory and controllers that perform low-level bad-block mapping and wear-leveling and logical-to-physical block mapping. The SCFD report their capacity, arrangement, and maximum wear-level count (WLC) and bad block number (BBN) to the upstream smart storage switch, which stores this information in a structure register. The smart storage switch selects the SCFD with the maximum BBN as the target and the SCFD with the lowest maximum WLC as the source of a swap for wear leveling when a WLC exceeds a threshold that rises over time. A top-level smart storage switch receives consolidated capacity, arrangement, WLC, and BBN information from lower-level smart storage switch. Data is striped and optionally scrambled by Redundant Array of Individual Disks (RAID) controllers in all levels of smart storage switches.
    • 智能闪存驱动器具有一个或多个级别的智能存储交换机和较低级别的单芯片闪存设备(SCFD)。 SCFD包含执行低级坏块映射和磨损均衡以及逻辑到物理块映射的闪存和控制器。 SCFD向上游智能存储交换机报告其容量,布置和最大磨损级数(WLC)和坏块号(BBN),将该信息存储在结构寄存器中。 智能存储交换机选择具有最大BBN作为目标的SCFD,而当WLC超过随时间上升的阈值时,具有最低最大WLC的SCFD作为用于损耗均衡的交换的来源。 顶级智能存储交换机从低级智能存储交换机接收统一的容量,安排,WLC和BBN信息。 数据是条带化的,并且可选地由所有级别的智能存储交换机中的冗余冗余阵列(RAID)控制器加扰。