专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20080295051A1 SLEW CONSTRAINED MINIMUM COST BUFFERING 有权
标题翻译： SLEW约束最小成本缓冲
公开(公告)号：US20080295051A1
公开(公告)日：2008-11-27
申请号：US12168153
申请日：2008-07-06
申请人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.
摘要翻译：缓冲插入技术解决了压摆约束，同时最大限度地减少了缓冲区成本。该方法构建了汇的初始解决方案，每个都具有相关的成本，压摆和电容。当解决方案向源传播时，将线电容和线压力加到解决方案中。当选择缓冲器进行可能的插入时，将解决方案的电压设置为零，同时根据所选择的缓冲器增加解决方案的成本，并将电容设置为缓冲器的固有电容。通过增加分支电容和成本，并选择最高的分支电压，合并两条相交线分支的解决方案。解决方案集通过忽略具有大于压摆约束的转矩分量的解决方案来更新，并且消除由另一解决方案主导的任何解决方案。选择具有最小成本的解决方案作为最终解决方案。

42. 发明申请

US20080148203A1 Latch Placement for High Performance and Low Power Circuits 有权
标题翻译：用于高性能和低功耗电路的锁存放置
公开(公告)号：US20080148203A1
公开(公告)日：2008-06-19
申请号：US11610567
申请日：2006-12-14
申请人： Charles J. Alpert , Shyam Ramji , Chin Ngai Sze , Paul G Villarrubia
发明人： Charles J. Alpert , Shyam Ramji , Chin Ngai Sze , Paul G Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A novel iterative latch placement scheme wherein the latches are gradually pulled by increasing attraction force until they are eventually placed next to a clock distribution structure such as a local clock buffer (LCB). During the iterations, timing optimizations such as gate sizing and re-buffering are invoked in order to keep the timing estimation accurate. By applying the iterative clock net weighting adjustment, the present invention allows tighter interaction between logic placement and clock placement which leads to higher quality timing and significant power savings.
摘要翻译：一种新颖的迭代锁存器放置方案，其中锁存器通过增加吸引力而逐渐拉动，直到它们最终被放置在诸如本地时钟缓冲器（LCB）之类的时钟分布结构旁边。在迭代期间，调用诸如门尺寸和重新缓冲之类的定时优化，以便使时序估计保持准确。通过应用迭代时钟网络加权调整，本发明允许逻辑放置和时钟布置之间的更紧密的交互，这导致更高的质量定时和显着的功率节省。

43. 发明授权

US06671867B2 Analytical constraint generation for cut-based global placement 有权
公开(公告)号：US06671867B2
公开(公告)日：2003-12-30
申请号：US10121877
申请日：2002-04-11
申请人： Charles J. Alpert , Gi-Joon Nam , Paul G. Villarrubia
发明人： Charles J. Alpert , Gi-Joon Nam , Paul G. Villarrubia
IPC分类号： G06F945
CPC分类号： G06F17/5072
摘要： A method of designing the layout of an integrated circuit (IC) by deriving an analytical constraint for a cut-based placement partitioner using analytical optimization, and placing cells on the IC with the cut-based placement partitioner using the analytical constraint. Quadratic optimization may be used to determine a desired ratio of a cell area of a given partition to a total cell area (the balance parameter), and placing may be performed using multilevel bisection partitioning constrained by the balance parameter. This implementation may include a determination of an aspect ratio for an entire partitioning region of the integrated circuit, and a “center-of-mass” coordinate of the cells based on the quadratic optimization, which are then used to define a placement rectangle having the same aspect ratio, and centered on the center-of-mass coordinate. This placement rectangle is used to derive the balance parameter. The placement rectangle has a total area equal to a total moveable cell area, and the balance parameter is computed by calculating the ratio of a left portion of the placement rectangle which lies in the left partition to the total area of the placement rectangle. The multilevel partitioner then places a proportionate number of the cells in the left partition based on the balance parameter.

44. 发明授权

US08495534B2 Post-placement cell shifting 失效
标题翻译：放置后细胞转移
公开(公告)号：US08495534B2
公开(公告)日：2013-07-23
申请号：US12796550
申请日：2010-06-08
申请人： Charles J. Alpert , Zhuo D. Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh E. Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo D. Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh E. Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块。扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。扩张器也可能使这些细胞膨胀并合法化。

45. 发明申请

US20120054708A1 ELECTRONIC DESIGN AUTOMATION OBJECT PLACEMENT WITH PARTIALLY REGION-CONSTRAINED OBJECTS 失效
标题翻译：具有部分约束对象的电子设计自动化对象放置
公开(公告)号：US20120054708A1
公开(公告)日：2012-03-01
申请号：US12870624
申请日：2010-08-27
申请人： Charles J. Alpert , John L. McCann , Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Natarajan Viswanathan
发明人： Charles J. Alpert , John L. McCann , Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A global placer receives a plurality of regions, each region occupying a sub-area of a design area. receives a plurality of movebound objects, each movebound object associated with a region. The global placer receives a plurality of unconstrained objects, each unconstrained object associated with no region. The global placer receives a tolerance, wherein the placement tolerance defines a coronal fringe to at least one region. The global placer initially placing the plurality of movebound objects and unconstrained objects. The global placer iterates over objects without preference to region-affiliation to select an object, wherein the objects are comprised of the plurality of movebound objects and plurality of unconstrained objects. The global placer determines whether movebound object is within the tolerance of a region associated with the movebound object.
摘要翻译：全局放置器接收多个区域，每个区域占据设计区域的子区域。接收多个移动对象，每个移动对象与一个区域相关联。全局放置器接收多个无约束对象，每个无约束对象与无区域相关联。全局放置器接收公差，其中放置公差将至少一个区域的冠状边缘定义。全局放置器最初放置多个移动对象和非约束对象。全局排列器迭代对象而不偏好区域属性来选择对象，其中对象由多个移动对象和多个无约束对象组成。全局置位器确定移动对象是否在与移动对象相关联的区域的公差范围内。

46. 发明授权

US07549137B2 Latch placement for high performance and low power circuits 有权
标题翻译：用于高性能和低功耗电路的锁存放置
公开(公告)号：US07549137B2
公开(公告)日：2009-06-16
申请号：US11610567
申请日：2006-12-14
申请人： Charles J. Alpert , Shyam Ramji , Chin Ngai Sze , Paul G. Villarrubia
发明人： Charles J. Alpert , Shyam Ramji , Chin Ngai Sze , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A novel iterative latch placement scheme wherein the latches are gradually pulled by increasing attraction force until they are eventually placed next to a clock distribution structure such as a local clock buffer (LCB). During the iterations, timing optimizations such as gate sizing and re-buffering are invoked in order to keep the timing estimation accurate. By applying the iterative clock net weighting adjustment, the present invention allows tighter interaction between logic placement and clock placement which leads to higher quality timing and significant power savings.
摘要翻译：一种新颖的迭代锁存器放置方案，其中锁存器通过增加吸引力而逐渐拉动，直到它们最终被放置在诸如本地时钟缓冲器（LCB）之类的时钟分布结构旁边。在迭代期间，调用诸如门尺寸和重新缓冲之类的定时优化，以便使时序估计保持准确。通过应用迭代时钟网络加权调整，本发明允许逻辑放置和时钟布置之间的更紧密的交互，这导致更高的质量定时和显着的功率节省。

47. 发明申请

US20090013299A1 BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS 审中-公开
标题翻译：缓冲插入减少VLSI电路中的WIRELENGTH
公开(公告)号：US20090013299A1
公开(公告)日：2009-01-08
申请号：US12207498
申请日：2008-09-10
申请人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F2217/84
摘要： Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.
摘要翻译：集成电路设计网络中的线长通过形成要互连的接收集群，在每个集群中插入缓冲区并通过将一个集群的接收器连接到另一个集群的缓冲区来提供集群之间的分支连接来减少，以创建一个跨越所有水槽的缓冲树。缓冲区被插入到最靠近网络源的簇的相应边界框上的点处。提供与另一个群集的缓冲区的分支连接的宿是与该缓冲区最接近的宿（除了群集中的那些宿）。可以通过用不同的边界框检查不同对的汇，并且将其边界框中具有最小半周的对中的一个作为聚类的最佳对来形成群集。

48. 发明申请

US20080066037A1 METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES BY MODULATION OF SPREADING FORCES VECTORS 审中-公开
标题翻译：通过扩展力矢量调制降低分析放置技术的线性的方法
公开(公告)号：US20080066037A1
公开(公告)日：2008-03-13
申请号：US11531322
申请日：2006-09-13
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of force directed placement programming is presented. The method includes sorting objects of a netlist for placement by magnitude of their spreading force and selecting a plurality of the objects. The method further includes waiving (or nullifying) the spreading force for the selected objects in a subsequent non-linear program solver step of the force directed placement program. The positions of the objects after the subsequent non-linear program solver step are based only on their connections to other objects in the netlist. The selected objects no longer retain their relative ordering as obtained during a previous non-linear program solve step of the force directed placement program. An alternative method of force directed placement programming is also present, which includes identifying objects from a netlist for placement that have a very high spreading force magnitude. The method further includes controlling the spreading force magnitude for the objects identified in the force directed placement programming to reduce wirelength in a chip design without sacrificing spreading of the objects.
摘要翻译：提出了一种强制定向布置程序的方法。该方法包括对网表的对象进行排序，以便按照其展开力的大小进行放置并选择多个对象。该方法还包括在力定向放置程序的随后非线性程序解算器步骤中放弃（或消除）所选对象的展开力。在后续非线性程序求解器步骤之后的对象的位置仅基于它们与网表中其他对象的连接。所选择的对象不再保留在力定向放置程序的先前非线性程序解决步骤中获得的相对排序。还存在一种替代的力定向放置编程的方法，其包括从具有非常高的铺展力量级的用于放置的网表识别对象。该方法还包括控制在力定向放置编程中识别的物体的展开力大小以减少芯片设计中的线长度，而不牺牲物体的扩展。

49. 发明申请

US20070271543A1 Buffer Insertion to Reduce Wirelength in VLSI Circuits 有权
标题翻译：缓冲插入以减少VLSI电路中的线长度
公开(公告)号：US20070271543A1
公开(公告)日：2007-11-22
申请号：US11383544
申请日：2006-05-16
申请人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F2217/84
摘要： Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.
摘要翻译：集成电路设计网络中的线长通过形成要互连的接收集群，在每个集群中插入缓冲区并通过将一个集群的接收器连接到另一个集群的缓冲区来提供集群之间的分支连接来减少，以创建一个跨越所有水槽的缓冲树。缓冲区被插入到最靠近网络源的簇的相应边界框上的点处。提供与另一个群集的缓冲区的分支连接的宿是与该缓冲区最接近的宿（除了群集中的那些宿）。可以通过用不同的边界框检查不同对的汇，并且将其边界框中具有最小半周的对中的一个作为聚类的最佳对来形成群集。

50. 发明授权

US08595675B1 Local objective optimization in global placement of an integrated circuit design 失效
标题翻译：集成电路设计的全局放置中的局部目标优化
公开(公告)号：US08595675B1
公开(公告)日：2013-11-26
申请号：US13539428
申请日：2012-06-30
申请人： Charles J. Alpert , Myung-Chul Kim , Gi-Joon Nam , Shyam Ramji , Natarajan Viswanathan
发明人： Charles J. Alpert , Myung-Chul Kim , Gi-Joon Nam , Shyam Ramji , Natarajan Viswanathan
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5072
摘要： A global placement phase of physical design of an integrated circuit includes iteratively spreading a plurality of modules comprising the integrated circuit within a die area based on density of the plurality of modules and optimizing module placement by preserving global module density while improving a local objective, such as local wirelength and/or local density, in individual subareas among a plurality of subareas of the die area. After global placement, detailed placement of modules in the plurality of subareas is performed.
摘要翻译：集成电路的物理设计的全局放置阶段包括基于多个模块的密度迭代地扩展包含该集成电路的多个模块，并且通过保持全局模块密度来优化模块放置，同时改善本地目标，例如作为模具区域的多个子区域中的各个子区域中的局部线长度和/或局部密度。在全局放置之后，执行在多个子区域中的模块的详细放置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式