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1. 发明申请

US20080282213A1 METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES BY MODULATION OF SPREADING FORCES VECTORS 有权
标题翻译：通过扩展力矢量调制降低分析放置技术的线性的方法
公开(公告)号：US20080282213A1
公开(公告)日：2008-11-13
申请号：US12181447
申请日：2008-07-29
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects.
摘要翻译：提出了一种强制定向布置程序的方法。该方法包括：将多个对象从小区网表分配给分组; 基于箱子移动物体; 基于所述移动来计算所述多个对象中的每个对象的扩展力的大小; 基于物体的展开力的大小对物体进行分类; 基于指示基于位置拥塞的最高百分比，阈值力和阈值中的至少一个的阈值来选择排序对象的子集; 将所选择的物体的展开力调整为等于表示最小铺展力的预定值; 以及基于所选择的对象的调整的展开力确定所述对象的位置。

2. 发明申请

US20080066037A1 METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES BY MODULATION OF SPREADING FORCES VECTORS 审中-公开
标题翻译：通过扩展力矢量调制降低分析放置技术的线性的方法
公开(公告)号：US20080066037A1
公开(公告)日：2008-03-13
申请号：US11531322
申请日：2006-09-13
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of force directed placement programming is presented. The method includes sorting objects of a netlist for placement by magnitude of their spreading force and selecting a plurality of the objects. The method further includes waiving (or nullifying) the spreading force for the selected objects in a subsequent non-linear program solver step of the force directed placement program. The positions of the objects after the subsequent non-linear program solver step are based only on their connections to other objects in the netlist. The selected objects no longer retain their relative ordering as obtained during a previous non-linear program solve step of the force directed placement program. An alternative method of force directed placement programming is also present, which includes identifying objects from a netlist for placement that have a very high spreading force magnitude. The method further includes controlling the spreading force magnitude for the objects identified in the force directed placement programming to reduce wirelength in a chip design without sacrificing spreading of the objects.
摘要翻译：提出了一种强制定向布置程序的方法。该方法包括对网表的对象进行排序，以便按照其展开力的大小进行放置并选择多个对象。该方法还包括在力定向放置程序的随后非线性程序解算器步骤中放弃（或消除）所选对象的展开力。在后续非线性程序求解器步骤之后的对象的位置仅基于它们与网表中其他对象的连接。所选择的对象不再保留在力定向放置程序的先前非线性程序解决步骤中获得的相对排序。还存在一种替代的力定向放置编程的方法，其包括从具有非常高的铺展力量级的用于放置的网表识别对象。该方法还包括控制在力定向放置编程中识别的物体的展开力大小以减少芯片设计中的线长度，而不牺牲物体的扩展。

3. 发明授权

US07882475B2 Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors 有权
标题翻译：通过调制扩展力矢量来减少分析放置技术的长度的方法
公开(公告)号：US07882475B2
公开(公告)日：2011-02-01
申请号：US12181447
申请日：2008-07-29
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072
摘要： A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects.
摘要翻译：提出了一种强制定向布置程序的方法。该方法包括：将多个对象从小区网表分配给分组; 基于箱子移动物体; 基于所述移动来计算所述多个对象中的每个对象的扩展力的大小; 基于物体的展开力的大小对物体进行分类; 基于指示基于位置拥塞的最高百分比，阈值力和阈值中的至少一个的阈值来选择排序对象的子集; 将所选择的物体的展开力调整为等于表示最小铺展力的预定值; 以及基于所选择的对象的调整的展开力确定所述对象的位置。

4. 发明授权

US07467369B2 Constrained detailed placement 有权
标题翻译：约束详细的布置
公开(公告)号：US07467369B2
公开(公告)日：2008-12-16
申请号：US11554235
申请日：2006-10-30
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072
摘要： The illustrative embodiments provide a computer implemented method which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set. The process performs a detailed placement transform by moving a subset of cells, making the placement legal, computing a half perimeter wire length change for each output net that is a member of the subset of nets, and computing a Manhattan distance change for each source-sink gate pair within the move cells. the process computes a weighted total wire length incremented value for the transformed data set. Further, the process continues by evaluating arrival time constraints, electrical constraints, and user configurable move limits for violations, and restoring the move cells to the original placement if a violation is found.
摘要翻译：说明性实施例提供了一种计算机实现的方法，其执行减小总线长度的小区变换，而不降低设备定时或违反电气约束。该过程计算数据集的延迟约束系数。该过程通过移动单元的子集来执行详细的放置变换，使得放置合法，计算作为网络子集成员的每个输出网的半周长线长度变化，以及计算每个源 - 移动细胞内的宿闸对。该过程计算用于变换数据集合的加权总线长度递增值。此外，该过程通过评估抵达时间约束，电气约束和用户可配置的违规移动限制，以及如果发现违规，则将移动单元恢复到原始位置继续。

5. 发明申请

US20080127017A1 CONSTRAINED DETAILED PLACEMENT 有权
标题翻译：约束的详细布置
公开(公告)号：US20080127017A1
公开(公告)日：2008-05-29
申请号：US11554235
申请日：2006-10-30
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method and a computer program product which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set. The process performs a detailed placement transform by moving a subset of cells, making the placement legal, computing a half perimeter wire length change for each output net that is a member of the subset of nets, and computing a Manhattan distance change for each source-sink gate pair within the move cells. The process computes a weighted total wire length incremented value for the transformed data set, if the move will not improve placement, the move transform is not allowed. Further, the process continues by evaluating arrival time constraints, electrical constraints and user configurable move limits for violations, restoring the move cells to the original placement if a violation is found.
摘要翻译：一种计算机实现的方法和一种计算机程序产品，其执行减少总线长度的小区变换，而不会降低设备定时或违反电气限制。该过程计算数据集的延迟约束系数。该过程通过移动单元的子集来执行详细的放置变换，使得放置合法，计算作为网络子集成员的每个输出网的半周长线长度变化，以及计算每个源 - 移动细胞内的宿闸对。该过程计算变换数据集的加权总线长度递增值，如果移动不会改善放置，则不允许移动变换。此外，该过程通过评估到达时间约束，电气约束和用户可配置的违规移动限制来继续，如果发现违规，则将移动单元恢复到原始位置。

6. 发明授权

US07624366B2 Clock aware placement 失效
标题翻译：时钟感知放置
公开(公告)号：US07624366B2
公开(公告)日：2009-11-24
申请号：US11554637
申请日：2006-10-31
申请人： Charles J. Alpert , David J. Hathaway , William R. Migatz , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
发明人： Charles J. Alpert , David J. Hathaway , William R. Migatz , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.
摘要翻译：锁存器在公共时钟域中的布局被有效优化，以缩小域的物理大小，同时保持时序要求。锁存器优选地使用二次放置放置在第一布局中，并且构建代表中间时钟结构的星形物体。锁存器根据与星形物体源的线距离进行加权，然后使用加权重新放置。可以迭代地重复加权放置和重新分配，直到达到目标数量的箱。最终全局放置中的锁存器的边界用于定义移动以进一步详细放置。

7. 发明申请

US20080127018A1 Clock Aware Placement 失效
标题翻译：时钟感知放置
公开(公告)号：US20080127018A1
公开(公告)日：2008-05-29
申请号：US11554637
申请日：2006-10-31
申请人： Charles J. Alpert , David J. Hathaway , William R. Migatz , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
发明人： Charles J. Alpert , David J. Hathaway , William R. Migatz , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.
摘要翻译：锁存器在公共时钟域中的布局被有效优化，以缩小域的物理大小，同时保持时序要求。锁存器优选地使用二次放置放置在第一布局中，并且构建代表中间时钟结构的星形物体。锁存器根据与星形物体源的线距离进行加权，然后使用加权重新放置。可以迭代地重复加权放置和重新分配，直到达到目标数量的箱。最终全局放置中的锁存器的边界用于定义移动以进一步详细放置。

8. 发明授权

US08112732B2 System and computer program product for diffusion based cell placement migration 有权
标题翻译：用于基于扩散的细胞置换迁移的系统和计算机程序产品
公开(公告)号：US08112732B2
公开(公告)日：2012-02-07
申请号：US12264619
申请日：2008-11-04
申请人： Charles J Alpert , Haoxing Ren , Paul Gerard Villarubia
发明人： Charles J Alpert , Haoxing Ren , Paul Gerard Villarubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system and computer program product for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces the density below a predetermined threshold. The method acts to control the movement of different cells to reduce the density of the cells prior to legalization of the cell placement.
摘要翻译：一种用于在集成电路设计中用于单元放置的系统和计算机程序产品，其使用从密度值确定的计算的扩散速度，以便重新定位单元直到单元布置将密度降低到低于预定阈值。该方法用于控制不同细胞的运动，以在细胞放置合法化之前降低细胞的密度。

9. 发明授权

US08566761B2 Network flow based datapath bit slicing 失效
标题翻译：基于网络流的数据路径位分片
公开(公告)号：US08566761B2
公开(公告)日：2013-10-22
申请号：US13301107
申请日：2011-11-21
申请人： Hua Xiang , Minsik Cho , Haoxing Ren , Matthew M Ziegler , Ruchir Puri
发明人： Hua Xiang , Minsik Cho , Haoxing Ren , Matthew M Ziegler , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/504
摘要： The present disclosure relates to a computer-based method and apparatus for determining datapath bit slices. A first two-way search is performed between an input vector and an output vector to identify gates in a datapath. A network flow is then constructed including the gates identified, and a min-cost max-flow algorithm is applied to the network flow to derive matching bit pairs between the input vector and the output vector. Next, the datapath bit slices are determined by performing a second two-way search between each of a starting bit in the input vector and an ending bit in the output vector of each of the matching bit pairs.
摘要翻译：本公开涉及一种用于确定数据路径位片的基于计算机的方法和装置。在输入向量和输出向量之间执行第一个双向搜索以识别数据通路中的门。然后构建包括所识别的门的网络流，并且将最小成本最大流算法应用于网络流以导出输入向量和输出向量之间的匹配比特对。接下来，通过在输入向量中的起始位和每个匹配位对的输出向量中的结束位之间执行第二双向搜索来确定数据通路位片。

10. 发明授权

US08516412B2 Soft hierarchy-based physical synthesis for large-scale, high-performance circuits 失效
标题翻译：用于大规模，高性能电路的基于层次结构的物理综合
公开(公告)号：US08516412B2
公开(公告)日：2013-08-20
申请号：US13222928
申请日：2011-08-31
申请人： Minsik Cho , Alvan W. Ng , Ruchir Puri , Haoxing Ren , Hua Xiang , Matthew M. Ziegler
发明人： Minsik Cho , Alvan W. Ng , Ruchir Puri , Haoxing Ren , Hua Xiang , Matthew M. Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/505
摘要： In one embodiment, the invention is a method and apparatus for soft hierarchy-based synthesis for large-scale, high-performance circuits. One embodiment of a method for physically synthesizing a design of an integrated circuit includes compiling a logical description of the design into a flattened netlist, extracting a soft hierarchy from the flattened netlist, wherein the soft hierarchy defines a boundary on a die across which cells of the integrated circuit are permitted to move, and placing a cell of the integrated circuit on the die in accordance with the soft hierarchy.
摘要翻译：在一个实施例中，本发明是用于大规模，高性能电路的基于层次的软合成的方法和装置。用于物理地合成集成电路的设计的方法的一个实施例包括将设计的逻辑描述编译成扁平网表，从扁平化网表中提取软层次，其中软层次结构定义了裸片上的边界，集成电路被允许移动，并且根据软层次将集成电路的单元放置在管芯上。

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