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1. 发明授权

US07467369B2 Constrained detailed placement 有权
标题翻译：约束详细的布置
公开(公告)号：US07467369B2
公开(公告)日：2008-12-16
申请号：US11554235
申请日：2006-10-30
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072
摘要： The illustrative embodiments provide a computer implemented method which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set. The process performs a detailed placement transform by moving a subset of cells, making the placement legal, computing a half perimeter wire length change for each output net that is a member of the subset of nets, and computing a Manhattan distance change for each source-sink gate pair within the move cells. the process computes a weighted total wire length incremented value for the transformed data set. Further, the process continues by evaluating arrival time constraints, electrical constraints, and user configurable move limits for violations, and restoring the move cells to the original placement if a violation is found.
摘要翻译：说明性实施例提供了一种计算机实现的方法，其执行减小总线长度的小区变换，而不降低设备定时或违反电气约束。该过程计算数据集的延迟约束系数。该过程通过移动单元的子集来执行详细的放置变换，使得放置合法，计算作为网络子集成员的每个输出网的半周长线长度变化，以及计算每个源 - 移动细胞内的宿闸对。该过程计算用于变换数据集合的加权总线长度递增值。此外，该过程通过评估抵达时间约束，电气约束和用户可配置的违规移动限制，以及如果发现违规，则将移动单元恢复到原始位置继续。

2. 发明申请

US20080282213A1 METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES BY MODULATION OF SPREADING FORCES VECTORS 有权
标题翻译：通过扩展力矢量调制降低分析放置技术的线性的方法
公开(公告)号：US20080282213A1
公开(公告)日：2008-11-13
申请号：US12181447
申请日：2008-07-29
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects.
摘要翻译：提出了一种强制定向布置程序的方法。该方法包括：将多个对象从小区网表分配给分组; 基于箱子移动物体; 基于所述移动来计算所述多个对象中的每个对象的扩展力的大小; 基于物体的展开力的大小对物体进行分类; 基于指示基于位置拥塞的最高百分比，阈值力和阈值中的至少一个的阈值来选择排序对象的子集; 将所选择的物体的展开力调整为等于表示最小铺展力的预定值; 以及基于所选择的对象的调整的展开力确定所述对象的位置。

3. 发明申请

US20080127017A1 CONSTRAINED DETAILED PLACEMENT 有权
标题翻译：约束的详细布置
公开(公告)号：US20080127017A1
公开(公告)日：2008-05-29
申请号：US11554235
申请日：2006-10-30
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method and a computer program product which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set. The process performs a detailed placement transform by moving a subset of cells, making the placement legal, computing a half perimeter wire length change for each output net that is a member of the subset of nets, and computing a Manhattan distance change for each source-sink gate pair within the move cells. The process computes a weighted total wire length incremented value for the transformed data set, if the move will not improve placement, the move transform is not allowed. Further, the process continues by evaluating arrival time constraints, electrical constraints and user configurable move limits for violations, restoring the move cells to the original placement if a violation is found.
摘要翻译：一种计算机实现的方法和一种计算机程序产品，其执行减少总线长度的小区变换，而不会降低设备定时或违反电气限制。该过程计算数据集的延迟约束系数。该过程通过移动单元的子集来执行详细的放置变换，使得放置合法，计算作为网络子集成员的每个输出网的半周长线长度变化，以及计算每个源 - 移动细胞内的宿闸对。该过程计算变换数据集的加权总线长度递增值，如果移动不会改善放置，则不允许移动变换。此外，该过程通过评估到达时间约束，电气约束和用户可配置的违规移动限制来继续，如果发现违规，则将移动单元恢复到原始位置。

4. 发明申请

US20130326455A1 ELEMENT PLACEMENT IN CIRCUIT DESIGN BASED ON PREFERRED LOCATION 有权
标题翻译：基于优选位置的电路设计中的元件放置
公开(公告)号：US20130326455A1
公开(公告)日：2013-12-05
申请号：US13485828
申请日：2012-05-31
申请人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F17/5081
摘要： An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.
摘要翻译：改进的电路设计系统可以包括计算机处理器，以通过物理合成来执行电路的放置。该系统还可以包括控制器，用于计算电路的至少一个选定元件的优选位置，并且计算每个选定元件的放置约束。该系统可以进一步包括通过用放置约束执行另一轮物理合成而产生的电路的更新设计。

5. 发明授权

US07882475B2 Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors 有权
标题翻译：通过调制扩展力矢量来减少分析放置技术的长度的方法
公开(公告)号：US07882475B2
公开(公告)日：2011-02-01
申请号：US12181447
申请日：2008-07-29
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072
摘要： A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects.
摘要翻译：提出了一种强制定向布置程序的方法。该方法包括：将多个对象从小区网表分配给分组; 基于箱子移动物体; 基于所述移动来计算所述多个对象中的每个对象的扩展力的大小; 基于物体的展开力的大小对物体进行分类; 基于指示基于位置拥塞的最高百分比，阈值力和阈值中的至少一个的阈值来选择排序对象的子集; 将所选择的物体的展开力调整为等于表示最小铺展力的预定值; 以及基于所选择的对象的调整的展开力确定所述对象的位置。

6. 发明授权

US08495534B2 Post-placement cell shifting 失效
标题翻译：放置后细胞转移
公开(公告)号：US08495534B2
公开(公告)日：2013-07-23
申请号：US12796550
申请日：2010-06-08
申请人： Charles J. Alpert , Zhuo D. Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh E. Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo D. Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh E. Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块。扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。扩张器也可能使这些细胞膨胀并合法化。

7. 发明授权

US08347257B2 Detailed routability by cell placement 有权
标题翻译：细胞放置的详细路线
公开(公告)号：US08347257B2
公开(公告)日：2013-01-01
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

8. 发明申请

US20110302544A1 POST-PLACEMENT CELL SHIFTING 失效
标题翻译：后置放电细胞移位
公开(公告)号：US20110302544A1
公开(公告)日：2011-12-08
申请号：US12796550
申请日：2010-06-08
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块。扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。扩张器也可能使这些细胞膨胀并合法化。

9. 发明申请

US20080066037A1 METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES BY MODULATION OF SPREADING FORCES VECTORS 审中-公开
标题翻译：通过扩展力矢量调制降低分析放置技术的线性的方法
公开(公告)号：US20080066037A1
公开(公告)日：2008-03-13
申请号：US11531322
申请日：2006-09-13
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of force directed placement programming is presented. The method includes sorting objects of a netlist for placement by magnitude of their spreading force and selecting a plurality of the objects. The method further includes waiving (or nullifying) the spreading force for the selected objects in a subsequent non-linear program solver step of the force directed placement program. The positions of the objects after the subsequent non-linear program solver step are based only on their connections to other objects in the netlist. The selected objects no longer retain their relative ordering as obtained during a previous non-linear program solve step of the force directed placement program. An alternative method of force directed placement programming is also present, which includes identifying objects from a netlist for placement that have a very high spreading force magnitude. The method further includes controlling the spreading force magnitude for the objects identified in the force directed placement programming to reduce wirelength in a chip design without sacrificing spreading of the objects.
摘要翻译：提出了一种强制定向布置程序的方法。该方法包括对网表的对象进行排序，以便按照其展开力的大小进行放置并选择多个对象。该方法还包括在力定向放置程序的随后非线性程序解算器步骤中放弃（或消除）所选对象的展开力。在后续非线性程序求解器步骤之后的对象的位置仅基于它们与网表中其他对象的连接。所选择的对象不再保留在力定向放置程序的先前非线性程序解决步骤中获得的相对排序。还存在一种替代的力定向放置编程的方法，其包括从具有非常高的铺展力量级的用于放置的网表识别对象。该方法还包括控制在力定向放置编程中识别的物体的展开力大小以减少芯片设计中的线长度，而不牺牲物体的扩展。

10. 发明授权

US09524363B2 Element placement in circuit design based on preferred location 有权
标题翻译：基于优选位置的电路设计元素放置
公开(公告)号：US09524363B2
公开(公告)日：2016-12-20
申请号：US13485828
申请日：2012-05-31
申请人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F17/5081
摘要： An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.
摘要翻译：改进的电路设计系统可以包括计算机处理器，以通过物理合成来执行电路的放置。该系统还可以包括控制器，用于计算电路的至少一个选定元件的优选位置，并且计算每个选定元件的放置约束。该系统可以进一步包括通过用放置约束执行另一轮物理合成而产生的电路的更新设计。

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