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41. 发明授权

US06977863B2 Device and method for decoding an address word into word-line signals 失效
公开(公告)号：US06977863B2
公开(公告)日：2005-12-20
申请号：US11051594
申请日：2005-02-04
申请人： Stefan Buettner , Jens Leenstra , Juergen Pille , Christian Schweizer
发明人： Stefan Buettner , Jens Leenstra , Juergen Pille , Christian Schweizer
IPC分类号： G11C7/10 , G11C8/10 , G11C8/00
CPC分类号： G11C8/10 , G11C7/1075
摘要： A method and a device for decoding an address word into word-line signals. A plurality of address lines feed the address word into a plurality of decoding blocks each associated to a particular address in the address space formed by the address word for generating a respective word-line signals, whereby each of the decoding blocks is connected to the plurality of address lines. At least one decoding block associated to a predetermined address in the address space formed by the address word is omitted, so that none of the generated word lines is switched to the active state, whenever the predetermined address word is inputted over the plurality of address lines.

42. 发明授权

US06725332B2 Hierarchical priority filter with integrated serialization for determining the entry with the highest priority in a buffer memory 失效
标题翻译：具有集成序列化的分层优先级过滤器，用于确定缓冲存储器中具有最高优先级的条目
公开(公告)号：US06725332B2
公开(公告)日：2004-04-20
申请号：US09681346
申请日：2001-03-22
申请人： Jens Leenstra , Antje Mueller , Juergen Pille , Dieter Wendel
发明人： Jens Leenstra , Antje Mueller , Juergen Pille , Dieter Wendel
IPC分类号： G06F1200
CPC分类号： G06F13/18
摘要： A storage device and a method for determining the entry with the highest priority in a buffer memory. The method is characterized by the steps of operating a plurality of priority subfilter circuits each of them covering a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority, and selecting the entry associated with the highest priority subgroup. The storage device is able to be allocated and deallocated repeatedly during processing program instructions in a computer system. The storage device is further characterized by an operator for operating a plurality of priority subfilter circuits. Each of priority subfilter circuits covers a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority. The storage device is still further characterized by a selector for selecting the entry associated with the highest priority subgroup.
摘要翻译：一种用于在缓冲存储器中确定具有最高优先级的条目的存储装置和方法。该方法的特征在于操作多个优先级子过滤器电路的步骤，每个优先级子过滤器电路覆盖总共条目的分离子组，并且每个选择具有最高子组优先级的条目，并且选择与最高优先级子组相关联的条目。在计算机系统中的处理程序指令期间，能够重新分配和释放存储设备。存储装置的特征还在于操作者操作多个优先级子滤波器电路。每个优先级子过滤器电路覆盖总共条目的分离子组，并且每个选择具有最高子组优先级的条目。存储装置的特征还在于：选择器，用于选择与最高优先级子组相关联的条目。

43. 发明授权

US06668341B1 Storage cell with integrated soft error detection and correction 失效
标题翻译：具有集成软错误检测和校正的存储单元
公开(公告)号：US06668341B1
公开(公告)日：2003-12-23
申请号：US09689968
申请日：2000-10-12
申请人： Ulrich Krauch , Antje Mueller , Juergen Pille , Dieter Wendel
发明人： Ulrich Krauch , Antje Mueller , Juergen Pille , Dieter Wendel
IPC分类号： G06F1100
CPC分类号： G11C29/74
摘要： Storage devices are presented which have some facility of error indication and error correction. The basic idea of the present invention is to double only the storing part inside the storing cell and share the environmental logic. Especially in case of multi-port cells this reduces the area penalty significantly because the read/write control within the cell is shared and only placed once. Writing the cell always writes both latches so that they hold the same data. A soft error can flip only one of the two latches. Then, a ‘XOR’ block detects that the data is no longer identical. While the data is read out the check bit indicates that the data is corrupted. The approach of doubling only the storing elements can be extended to implement a triple storing element (10, 12, 30) in the same cell. Then, with the help of a small and simple error correction logic (32) in the cell from a ‘majority vote’ can be seen which bit value is wrong in case of a soft error affecting one bit in the cell. Thus, no post-processing is necessary after reading the bit from the cell, as it is true per se. (FIG. 3).
摘要翻译：给出了具有错误指示和错误校正功能的存储设备。本发明的基本思想是将存储单元内的存储部分加倍，并共享环境逻辑。特别是在多端口单元的情况下，由于单元内的读/写控制是共享的，只能放置一次，因此这会大大减少面积损失。写单元格总是写入两个锁存器，以便它们保存相同的数据。软错误只能翻转两个锁存器之一。然后，“异或”块检测到数据不再相同。读出数据时，校验位表示数据已损坏。可以扩展仅存储元件加倍的方法，以在同一单元中实现三重存储元件（10,12,30）。然后，借助于“多数投票”的单元格中的小而简单的纠错逻辑（32），可以看出在单元格中影响一位的软错误的情况下哪个位值是错误的。因此，从单元读取位之后，不需要进行后处理，因为它本身是真实的。（图3）。

44. 发明授权

US06629215B2 Multiple port memory apparatus 失效
标题翻译：多端口存储设备
公开(公告)号：US06629215B2
公开(公告)日：2003-09-30
申请号：US09811916
申请日：2001-03-19
申请人： Juergen Pille , Rolf Sautter , Dieter Wendel , George M. Lattimore
发明人： Juergen Pille , Rolf Sautter , Dieter Wendel , George M. Lattimore
IPC分类号： G06F1200
CPC分类号： G06F9/30141 , G11C7/1006 , G11C7/1012 , G11C7/22 , G11C2207/229 , Y10S707/99953 , Y10S707/99954
摘要： In order to provide an improved wiring management approach, a multiple port memory apparatus (200) is proposed, which comprises a first memory field of a first memory array (201) of at least three memory arrays (201, 202, 203) storing first data, wherein the first memory field is identified by a first address, a first memory field of a second memory array (202) of the at least three memory arrays (201, 202, 203) storing second data, wherein the first memory field of the second memory array (202) is also identified by the first address, and a first memory field of a third memory array (203) of the at least three memory arrays (201, 202, 203) storing select data indicating, whether the first data or the second data, each stored under the first address but in different memory arrays, have been lastly written.
摘要翻译：为了提供改进的布线管理方法，提出了一种多端口存储装置（200），其包括至少存储有第一存储器阵列（201,202,203）的第一存储器阵列（201）的第一存储器阵列（201,202,203）数据，其中第一存储器字段由第一地址识别，存储第二数据的至少三个存储器阵列（201,202,203）的第二存储器阵列（202）的第一存储器字段，其中第一存储器字段所述第二存储器阵列（202）也由所述第一地址标识，并且所述至少三个存储器阵列（201,202,203）中的第三存储器阵列（203）的第一存储器字段存储选择数据，所述选择数据指示所述第一存储器阵列最后写入数据或第二数据，每个存储在第一地址但不同的存储器阵列中。

45. 发明授权

US06614265B2 Static logic compatible multiport latch 失效
公开(公告)号：US06614265B2
公开(公告)日：2003-09-02
申请号：US09683260
申请日：2001-12-05
申请人： Stefan Buettner , Guenter Mayer , Juergen Pille , Dieter Wendel
发明人： Stefan Buettner , Guenter Mayer , Juergen Pille , Dieter Wendel
IPC分类号： H03K1900
CPC分类号： H03K3/356156 , H03K3/356121 , H03K17/005 , H03K17/693
摘要： The invention describes a high-performance static logic compatible multiport latch. The latch is controlled by at least a first and a second clock (CLK 1, CLK 2), which consist of at least first and second data input ports (107, 111) with together at least three data inputs (DATA 1.1, . . . , DATA 1.n, DATA 2.1, . . . , DATA 2.n) and at least one data output (OUT). The first clock (CLK 1) controls whether data (DATA1.1, . . . , DATA 1.n) applied to the first data input ports (107) is stored in or clocked through the latch (100), the second clock (CLK 2) controls whether data (DATA 2.1, . . . , DATA 2.n) applied to the second data input ports (111) is stored in or clocked through the latch, and either the first clock (CLK 1) or the second clock (CLK 2) clocks data into the latch at the same time.

46. 发明授权

US07921388B2 Wordline booster design structure and method of operating a wordine booster circuit 有权
标题翻译： Wordline助推器设计结构和操作字提升电路的方法
公开(公告)号：US07921388B2
公开(公告)日：2011-04-05
申请号：US11847759
申请日：2007-08-30
申请人： Sebastian Ehrenreich , Juergen Pille , Otto Torreiter
发明人： Sebastian Ehrenreich , Juergen Pille , Otto Torreiter
IPC分类号： G06F17/50 , G11C16/06
CPC分类号： G11C5/145 , G11C8/08 , G11C11/413
摘要： The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of a charging element (40), wherein the charging element (40) is actively switchable between a turned-off state during a first time interval and a turned-on state during a second time interval, and an output port (14) for supplying the boost voltage to at least one wordline-driver circuit (100) of a memory device (200). The invention relates also to an operation method for such a wordline booster circuit as well as a memory array implementation on an integrated circuit, especially an SRAM memory array, with a wordline booster circuit.
摘要翻译：本发明涉及一种字线升压电路，特别是一种SRAM字线升压电路，它包括用于移动电荷存储元件（50）的电压电平的驱动元件（20），用于存储产生升压电压（Vb）所需的电荷，，用于控制充电元件（40）的开关状态的反馈元件（30），其中所述充电元件（40）可在第一时间间隔期间的关断状态和第二时间间隔期间的接通状态之间主动切换以及用于将升压电压提供给存储装置（200）的至少一个字线驱动电路（100）的输出端口（14）。本发明还涉及这种字线升压电路的操作方法以及具有字线升压电路的集成电路，特别是SRAM存储器阵列上的存储器阵列实现。

47. 发明授权

US07844871B2 Test interface for memory elements 失效
标题翻译：测试界面的内存元素
公开(公告)号：US07844871B2
公开(公告)日：2010-11-30
申请号：US12268903
申请日：2008-11-11
申请人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
发明人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/32 , G11C2029/3202
摘要： A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.
摘要翻译：一种用于测试具有内置于自检（ABIST）中的阵列的集成电路的存储器元件的方法，包括提供ABIST接口以在ABIST引擎和被测存储元件的多个锁存器之间进行接口，提供多路复用（MUX）级邻近每个锁存器的扫描输入端口，向锁存器的数据输入端口提供功能信号输入，通过激活ABIST使能信号并将ABIST使能信号传送到每个锁存器，将锁存器设置为ABIST模式，产生多个的ABIST测试信号与ABIST引擎并行地应用ABIST测试信号并且与锁存器的扫描输入端口并行，确定是否执行了一个或多个测试模式，并通过停用ABIST使能来将锁存器设置为正常运行模式信号。

48. 发明授权

US07760541B2 Functional float mode screen to test for leakage defects on SRAM bitlines 失效
标题翻译：功能浮动模式屏幕，用于测试SRAM位线上的漏电缺陷
公开(公告)号：US07760541B2
公开(公告)日：2010-07-20
申请号：US12190242
申请日：2008-08-12
申请人： Chad A Adams , Juergen Pille
发明人： Chad A Adams , Juergen Pille
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1204 , G11C2029/5006
摘要： A method and system for maintaining Static Random Access Memory (SRAM) functionality while simultaneously screening for leakage paths from bitline to ground during Float Mode operation. The SRAM configuration enables SRAM cell selection for a read or write operation. In response to the SRAM cell selection, a group of pre-charge (PCHG) signals are provided with a high value. When selection is made from a top sub-group of SRAM cells, a corresponding bitline, “BLT_TOP”, takes a value which reflects a state stored in the selected cell. In addition, the bitline corresponding to the bottom sub-group of cells, “BLT_BOT”, takes a high value. If there is a leakage defect, BLT_BOT drops to a low value. With no leakage defect, the data stored in the selected cell is determined based on the result of a logical NAND operation including the respective states indicated by the BLT_TOP and by the BLT_BOT.
摘要翻译：一种用于保持静态随机存取存储器（SRAM）功能的方法和系统，同时在浮动模式操作期间同时筛选从位线到地的泄漏路径。 SRAM配置允许SRAM单元选择进行读或写操作。响应于SRAM单元选择，提供一组具有高值的预充电（PCHG）信号。当从SRAM单元的顶部子组进行选择时，对应的位线“BLT_TOP”取反映存储在所选单元中的状态的值。另外，对应于单元格底部子组“BLT_BOT”的位线取高值。如果存在泄漏缺陷，BLT_BOT将降至低值。在没有泄漏缺陷的情况下，基于包括由BLT_TOP指示的各个状态和BLT_BOT的逻辑NAND操作的结果来确定存储在所选择的单元中的数据。

49. 发明授权

US07755408B2 Redundancy in signal distribution trees 有权
标题翻译：信号分配树的冗余
公开(公告)号：US07755408B2
公开(公告)日：2010-07-13
申请号：US11868637
申请日：2007-10-08
申请人： Sebastian Ehrenreich , Juergen Koehl , Juergen Pille
发明人： Sebastian Ehrenreich , Juergen Koehl , Juergen Pille
IPC分类号： G06F1/04 , H03K1/04
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/007
摘要： A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/our preceding sub tree.
摘要翻译：一种信号分配树结构，用于将多个信号树分支中的信号分配到多个信号宿，其中后续子树（11）中的信号由前一放大器（2）驱动，其特征在于放大器是逻辑门（3），其将连接到信号路径中的先前逻辑门的优选输入（31）的信号与连接到邻近的相邻树（12）路径的次级输入（32）的信号组合，以及 /我们以前的子树。

50. 发明申请

US20100122128A1 TEST INTERFACE FOR MEMORY ELEMENTS 失效
标题翻译：记忆元素的测试界面
公开(公告)号：US20100122128A1
公开(公告)日：2010-05-13
申请号：US12268903
申请日：2008-11-11
申请人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
发明人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/16 , G11C29/32 , G11C2029/3202
摘要： A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.
摘要翻译：一种用于测试具有内置于自检（ABIST）中的阵列的集成电路的存储器元件的方法，包括提供ABIST接口以在ABIST引擎和被测存储元件的多个锁存器之间进行接口，提供多路复用（MUX）级邻近每个锁存器的扫描输入端口，向锁存器的数据输入端口提供功能信号输入，通过激活ABIST使能信号并将ABIST使能信号传送到每个锁存器，将锁存器设置为ABIST模式，产生多个的ABIST测试信号与ABIST引擎并行地应用ABIST测试信号并且与锁存器的扫描输入端口并行，确定是否执行了一个或多个测试模式，并通过停用ABIST使能来将锁存器设置为正常运行模式信号。

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