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41. 发明申请

US20120235216A1 DAMASCENE METAL GATE AND SHIELD STRUCTURE, METHODS OF MANUFACTURE AND DESIGN STRUCTURES 有权
标题翻译：大金属门和屏蔽结构，制造和设计结构的方法
公开(公告)号：US20120235216A1
公开(公告)日：2012-09-20
申请号：US13051510
申请日：2011-03-18
申请人： Brent A. ANDERSON , Andres Bryant , William F. Clark, JR. , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. ANDERSON , Andres Bryant , William F. Clark, JR. , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L31/0216 , G06F17/50 , H01L31/18
CPC分类号： H01L31/0232 , G06F17/5045 , G06F17/5054 , H01L27/14632 , H01L27/14683 , H01L29/66545
摘要： Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses.
摘要翻译：提供了具有镶嵌金属栅极和像素传感器单元屏蔽的半导体结构，制造方法和设计结构。该方法包括在虚拟栅极结构上形成介电层。该方法还包括在电介质层中形成一个或多个凹槽。该方法还包括去除电介质层中的虚拟栅极结构以形成沟槽。该方法还包括在沟槽中形成金属和在电介质层中形成多个凹槽以在沟槽中形成镶嵌金属栅极结构以及在一个或多个凹槽中形成一个或多个金属部件。

42. 发明申请

US20120190156A1 RECESSED GATE CHANNEL WITH LOW Vt CORNER 有权
标题翻译：具有低Vt角的后门通道
公开(公告)号：US20120190156A1
公开(公告)日：2012-07-26
申请号：US13363944
申请日：2012-02-01
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L29/1083 , H01L29/4236 , H01L29/517 , H01L29/66621 , H01L29/78
摘要： A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region.
摘要翻译：凹陷栅极FET器件包括具有上部和下部的衬底，下部具有比上部更低的掺杂剂材料的浓度; 限定周围通道区域并且具有衬底的栅介质材料层的沟槽型栅电极，并且包括具有凹陷的顶表面的导电材料，以减少相对于在上基板表面处形成的源极和漏极扩散区域的重叠电容侧电极。在栅电极的任一侧和邻接栅电极处可选地形成卤素植入物，每个卤素注入物延伸到源极和漏极扩散到沟道区域之内。此外，形成高掺杂的源极和漏极延伸区域，其提供从源极和漏极扩散区域到沟道区域的低电阻路径。

43. 发明申请

US20120168832A1 ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 有权
标题翻译：不对称场效应晶体管结构与方法
公开(公告)号：US20120168832A1
公开(公告)日：2012-07-05
申请号：US13246175
申请日：2011-09-27
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
摘要翻译：公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供改进的驱动电流，电路延迟最小）。具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。

44. 发明申请

US20120146146A1 PARTIALLY DEPELETED (DP) SEMICONDUCTOR-ON-INSULATOR (SOI) FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH A GATE-TO-BODY TUNNEL CURRENT REGION FOR THRESHOLD VOLTAGE (Vt) LOWERING AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：具有门控电压（Vt）的栅极 - 体积隧道电流区域（DP）半导体绝缘体（SOI）场效应晶体管（FET）结构和形成结构的方法
公开(公告)号：US20120146146A1
公开(公告)日：2012-06-14
申请号：US12967329
申请日：2010-12-14
申请人： Brent A. Anderson , Andres Bryant , Jiale Liang , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Jiale Liang , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L21/26506 , H01L29/32 , H01L29/66477 , H01L29/78612
摘要： Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.
摘要翻译：公开了具有栅对体隧道电流区域（GTBTCR）的场效应晶体管的实施例和方法。在一个实施例中，具有不同导电类型的相邻部分的栅极穿过半导体层的中心部分，以在中心部分内分别在具有不同导电类型的相邻部分之下分别形成沟道区域和GTBTCR。在另一个实施例中，半导体层具有具有沟道区域的中心部分和GTBTCR。 GTBTCR包括：与沟道区相邻并掺杂相同的第一导电类型掺杂剂的较高浓度的第一注入区; 具有第二导电类型的与第一植入区相邻的第二植入区; 以及植入区域之间的增强的生成和重组区域。具有第二导电类型的栅极穿过中心部分。

45. 发明授权

US08198682B2 Semiconductor structure having a gate electrode at least partially disposed in a trench formed at a bend in a semiconductor material 有权
标题翻译：半导体结构具有至少部分地设置在半导体材料的弯曲处形成的沟槽中的栅电极
公开(公告)号：US08198682B2
公开(公告)日：2012-06-12
申请号：US12875416
申请日：2010-09-03
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/31155 , H01L21/76283 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1203 , H01L29/1037 , H01L29/66621 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.
摘要翻译：一种包括半导体材料的半导体器件，该半导体材料具有形成在该弯曲处的弯曲部和沟槽特征，以及至少部分地设置在沟槽特征中的栅极结构。一种制造半导体结构的方法，包括在层上形成具有沟槽特征的半导体材料，在沟槽特征中至少部分地形成栅极结构，以及弯曲半导体材料，使得在反转沟道中的半导体材料中产生应力栅结构的区域。

46. 发明授权

US08193067B2 Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit 有权
标题翻译：集成电路和采用集成工艺步骤形成集成电路的深沟槽隔离结构和深沟槽电容器结构的方法
公开(公告)号：US08193067B2
公开(公告)日：2012-06-05
申请号：US12630091
申请日：2009-12-03
申请人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
IPC分类号： H01L21/20
CPC分类号： H01L21/76224 , H01L27/10829 , H01L27/10867 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).
摘要翻译：公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

47. 发明申请

US20110133310A1 INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT 有权
标题翻译：集成电路和使用集成工艺步骤形成集成电路的深层隔离分离结构和深层电容电容器结构的方法
公开(公告)号：US20110133310A1
公开(公告)日：2011-06-09
申请号：US12630091
申请日：2009-12-03
申请人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
IPC分类号： H01L29/92 , H01L21/8242
CPC分类号： H01L21/76224 , H01L27/10829 , H01L27/10867 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).
摘要翻译：公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

48. 发明授权

US07939417B2 Bipolar transistor and back-gated transistor structure and method 有权
标题翻译：双极晶体管和后栅晶体管结构及方法
公开(公告)号：US07939417B2
公开(公告)日：2011-05-10
申请号：US12536636
申请日：2009-08-06
申请人： Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
发明人： Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
IPC分类号： H01L21/331
CPC分类号： H01L21/84 , H01L21/8249 , H01L27/0623 , H01L27/1203 , H01L29/0804 , H01L29/7327 , H01L29/78648
摘要： A structure is disclosed including a substrate including an insulator layer on a bulk layer, and a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer. Another disclosed structure includes an inverted bipolar transistor in a first region of a substrate including an insulator layer on a bulk layer, the inverted bipolar transistor including an emitter region, and a back-gated transistor in a second region of the substrate, wherein a back-gate conductor of the back-gated transistor and at least a portion of the emitter region are in the same layer of material. A method of forming the structures including a bipolar transistor and back-gated transistor together is also disclosed.
摘要翻译：公开了一种结构，其包括在体层上包括绝缘体层的衬底和在衬底的第一区域中的双极晶体管，所述双极晶体管包括绝缘体层中的发射极区域的至少一部分。另一公开的结构包括在衬底的第一区域中的反相双极晶体管，其包括体层上的绝缘体层，反相双极晶体管包括发射极区域，以及位于衬底的第二区域中的后栅极晶体管，其中背面背栅式晶体管的栅极导体和发射极区域的至少一部分处于相同的材料层中。还公开了一种将双极晶体管和后栅极晶体管组合在一起的结构的方法。

49. 发明申请

US20110068414A1 INTEGRATED CIRCUIT DEVICE WITH SERIES-CONNECTED FIN-TYPE FIELD EFFECT TRANSISTORS AND INTEGRATED VOLTAGE EQUALIZATION AND METHOD OF FORMING THE DEVICE 失效
标题翻译：具有串联型FIN型场效应晶体管和集成电压均衡的集成电路装置及其形成方法
公开(公告)号：US20110068414A1
公开(公告)日：2011-03-24
申请号：US12563194
申请日：2009-09-21
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/785 , H01L29/66795
摘要： Disclosed is an integrated circuit device having stacked fin-type field effect transistors (FINFETs) with integrated voltage equalization and a method. A multi-layer fin includes a semiconductor layer, an insulator layer above the semiconductor layer and a high resistance conductor layer above the insulator layer. For each FINFET, a gate is positioned on the sidewalls and top surface of the fin and source/drain regions are within the semiconductor layer on both sides of the gate. Thus, the portion of the semiconductor layer between any two gates contains a source/drain region of one FINFET abutting a source/drain region of another. Conductive straps are positioned on opposing ends of the fin and also between adjacent gates in order to electrically connect the semiconductor layer to the conductor layer. Contacts electrically connect the conductive straps at the opposing ends of the fin to positive and negative supply voltages, respectively.
摘要翻译：公开了具有集成电压均衡的堆叠鳍式场效应晶体管（FINFET）的集成电路器件和方法。多层翅片包括半导体层，半导体层上方的绝缘体层和绝缘体层上方的高电阻导体层。对于每个FINFET，栅极位于鳍的侧壁和顶表面上，并且源/漏区在栅极两侧的半导体层内。因此，任何两个栅极之间的半导体层的部分包含邻接另一栅极的源极/漏极区域的一个FINFET的源极/漏极区域。导电带位于鳍的相对端并且还位于相邻栅之间，以将半导体层电连接到导体层。触头将鳍片的相对端处的导电带分别电连接到正和负电源电压。

50. 发明授权

US07843016B2 Asymmetric field effect transistor structure and method 有权
标题翻译：不对称场效应晶体管结构及方法
公开(公告)号：US07843016B2
公开(公告)日：2010-11-30
申请号：US11869145
申请日：2007-10-09
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments for a design structure of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
摘要翻译：公开了用于非对称场效应晶体管结构的设计结构的实施例以及形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即，以最小的电路延迟来提供改进的驱动电流）。具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。

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