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41. 发明授权

US10152450B2 Remote processing and memory utilization 有权
公开(公告)号：US10152450B2
公开(公告)日：2018-12-11
申请号：US13584323
申请日：2012-08-13
申请人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F15/167 , G06F15/173 , G06F9/54 , H04L29/06 , H04L29/08
摘要： According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.

42. 发明申请

US20110173421A1 MULTI-INPUT AND BINARY REPRODUCIBLE, HIGH BANDWIDTH FLOATING POINT ADDER IN A COLLECTIVE NETWORK 有权
标题翻译：多输入和二进制可复现，集合网络中的高带宽浮点添加
公开(公告)号：US20110173421A1
公开(公告)日：2011-07-14
申请号：US12684776
申请日：2010-01-08
申请人： Dong Chen , Noel A. Eisley , Philip Heidelberger , Burkhard Steinmacher-Burow
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger , Burkhard Steinmacher-Burow
IPC分类号： G06F9/302
CPC分类号： G06F7/38 , G06F7/485 , G06F9/30014 , G06F9/30025 , G06F9/3885 , G06F2207/3808
摘要： To add floating point numbers in a parallel computing system, a collective logic device receives the floating point numbers from computing nodes. The collective logic devices converts the floating point numbers to integer numbers. The collective logic device adds the integer numbers and generating a summation of the integer numbers. The collective logic device converts the summation to a floating point number. The collective logic device performs the receiving, the converting the floating point numbers, the adding, the generating and the converting the summation in one pass. One pass indicates that the computing nodes send inputs only once to the collective logic device and receive outputs only once from the collective logic device.
摘要翻译：为了在并行计算系统中添加浮点数，集体逻辑器件从计算节点接收浮点数。集体逻辑器件将浮点数转换为整数。集体逻辑器件添加整数并产生整数的求和。集体逻辑设备将求和转换为浮点数。集体逻辑设备执行接收，转换浮点数，加法，生成和一次转换求和。一次通过表示计算节点仅向集体逻辑设备发送一次输入，并从集体逻辑设备接收一次输出。

43. 发明授权

US09037669B2 Remote processing and memory utilization 有权
标题翻译：远程处理和内存利用
公开(公告)号：US09037669B2
公开(公告)日：2015-05-19
申请号：US13570916
申请日：2012-08-09
申请人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F15/167 , G06F15/173 , G06F11/00 , G06F9/54 , H04L29/06
CPC分类号： G06F9/547 , H04L29/0617 , H04L67/40
摘要： According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.
摘要翻译：根据本发明的一个实施例，一种用于操作存储器的系统包括由网络耦合到第二节点的第一节点，所述系统被配置为执行一种方法，该方法包括从所述第二节点接收来自所述第二节点的处理元件中的所述远程事务消息第一节点经由网络，其中当所述远程事务消息被传送到所述处理元件时，所述远程事务消息绕过所述第一节点中的主处理器。此外，该方法包括基于远程事务消息，由处理元件访问来自第一节点中的存储器中的位置的数据，以及由处理元件基于数据和远程事务消息执行计算。

44. 发明授权

US08977669B2 Multi-input and binary reproducible, high bandwidth floating point adder in a collective network 有权
标题翻译：集成网络中的多输入和二进制可重复的高带宽浮点加法器
公开(公告)号：US08977669B2
公开(公告)日：2015-03-10
申请号：US12684776
申请日：2010-01-08
申请人： Dong Chen , Noel A. Eisley , Philip Heidelberger , Burkhard Steinmacher-Burow
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger , Burkhard Steinmacher-Burow
IPC分类号： G06F7/38 , G06F9/30 , G06F9/38
CPC分类号： G06F7/38 , G06F7/485 , G06F9/30014 , G06F9/30025 , G06F9/3885 , G06F2207/3808
摘要： To add floating point numbers in a parallel computing system, a collective logic device receives the floating point numbers from computing nodes. The collective logic devices converts the floating point numbers to integer numbers. The collective logic device adds the integer numbers and generating a summation of the integer numbers. The collective logic device converts the summation to a floating point number. The collective logic device performs the receiving, the converting the floating point numbers, the adding, the generating and the converting the summation in one pass. One pass indicates that the computing nodes send inputs only once to the collective logic device and receive outputs only once from the collective logic device.
摘要翻译：为了在并行计算系统中添加浮点数，集体逻辑器件从计算节点接收浮点数。集体逻辑器件将浮点数转换为整数。集体逻辑器件添加整数并产生整数的求和。集体逻辑设备将求和转换为浮点数。集体逻辑设备执行接收，转换浮点数，加法，生成和一次转换求和。一次通过表示计算节点仅向集体逻辑设备发送一次输入，并从集体逻辑设备接收一次输出。

45. 发明授权

US08381230B2 Message passing with queues and channels 失效
标题翻译：消息传递与队列和通道
公开(公告)号：US08381230B2
公开(公告)日：2013-02-19
申请号：US12764315
申请日：2010-04-21
申请人： Gabor J. Dozsa , Philip Heidelberger , Sameer Kumar , Joseph D. Ratterman , Burkhard Steinmacher-Burow
发明人： Gabor J. Dozsa , Philip Heidelberger , Sameer Kumar , Joseph D. Ratterman , Burkhard Steinmacher-Burow
IPC分类号： G06F3/00
CPC分类号： G06F9/546 , G06F2209/548
摘要： In an embodiment, a reception thread receives a source node identifier, a type, and a data pointer from an application and, in response, creates a receive request. If the source node identifier specifies a source node, the reception thread adds the receive request to a fast-post queue. If a message received from a network does not match a receive request on a posted queue, a polling thread adds a receive request that represents the message to an unexpected queue. If the fast-post queue contains the receive request, the polling thread removes the receive request from the fast-post queue. If the receive request that was removed from the fast-post queue does not match the receive request on the unexpected queue, the polling thread adds the receive request that was removed from the fast-post queue to the posted queue. The reception thread and the polling thread execute asynchronously from each other.
摘要翻译：在一个实施例中，接收线程从应用接收源节点标识符，类型和数据指针，作为响应，创建接收请求。如果源节点标识符指定源节点，则接收线程将接收请求添加到快速发送队列。如果从网络接收到的消息与发布的队列上的接收请求不匹配，轮询线程将将消息的接收请求添加到意外队列。如果快速发送队列包含接收请求，轮询线程将从快速发送队列中删除接收请求。如果从快速发布队列中删除的接收请求与意外队列中的接收请求不匹配，轮询线程将从快速发布队列中删除的接收请求添加到发布的队列。接收线程和轮询线程彼此异步执行。

46. 发明授权

US07802025B2 DMA engine for repeating communication patterns 失效
标题翻译：用于重复通信模式的DMA引擎
公开(公告)号：US07802025B2
公开(公告)日：2010-09-21
申请号：US11768795
申请日：2007-06-26
申请人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard Steinmacher-Burow , Pavlos Vranas
发明人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F15/163
摘要： A parallel computer system is constructed as a network of interconnected compute nodes to operate a global message-passing application for performing communications across the network. Each of the compute nodes includes one or more individual processors with memories which run local instances of the global message-passing application operating at each compute node to carry out local processing operations independent of processing operations carried out at other compute nodes. Each compute node also includes a DMA engine constructed to interact with the application via Injection FIFO Metadata describing multiple Injection FIFOs where each Injection FIFO may containing an arbitrary number of message descriptors in order to process messages with a fixed processing overhead irrespective of the number of message descriptors included in the Injection FIFO.
摘要翻译：并行计算机系统被构造为互连的计算节点的网络，以操作用于在整个网络上执行通信的全局消息传递应用。每个计算节点包括具有存储器的一个或多个单独处理器，该存储器运行在每个计算节点处操作的全局消息传递应用的本地实例，以独立于在其他计算节点执行的处理操作来执行本地处理操作。每个计算节点还包括构造成通过描述多个注入FIFO的注入FIFO元数据与应用交互的DMA引擎，其中每个注入FIFO可以包含任意数量的消息描述符，以便处理具有固定处理开销的消息，而不管消息的数量描述符包含在注入FIFO中。

47. 发明申请

US20130290473A1 REMOTE PROCESSING AND MEMORY UTILIZATION 审中-公开
标题翻译：远程处理和存储器的使用
公开(公告)号：US20130290473A1
公开(公告)日：2013-10-31
申请号：US13584323
申请日：2012-08-13
申请人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F15/167
CPC分类号： G06F15/17331 , G06F9/544 , H04L29/0617 , H04L67/1097
摘要： According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.
摘要翻译：根据本发明的一个实施例，一种用于操作存储器的系统包括由网络耦合到第二节点的第一节点，所述系统被配置为执行一种方法，该方法包括从所述第二节点接收来自所述第二节点的处理元件中的所述远程事务消息第一节点经由网络，其中当所述远程事务消息被传送到所述处理元件时，所述远程事务消息绕过所述第一节点中的主处理器。此外，该方法包括基于远程事务消息，由处理元件访问来自第一节点中的存储器中的位置的数据，以及由处理元件基于数据和远程事务消息执行计算。

48. 发明授权

US08364844B2 Deadlock-free class routes for collective communications embedded in a multi-dimensional torus network 失效
标题翻译：嵌套在多维环面网络中的集体通信的无死锁级路由
公开(公告)号：US08364844B2
公开(公告)日：2013-01-29
申请号：US12697015
申请日：2010-01-29
申请人： Dong Chen , Noel A. Eisley , Burkhard Steinmacher-Burow , Philip Heidelberger
发明人： Dong Chen , Noel A. Eisley , Burkhard Steinmacher-Burow , Philip Heidelberger
IPC分类号： G06F15/173
CPC分类号： G06F15/17381 , G06F9/30072
摘要： A computer implemented method and a system for routing data packets in a multi-dimensional computer network. The method comprises routing a data packet among nodes along one dimension towards a root node, each node having input and output communication links, said root node not having any outgoing uplinks, and determining at each node if the data packet has reached a predefined coordinate for the dimension or an edge of the subrectangle for the dimension, and if the data packet has reached the predefined coordinate for the dimension or the edge of the subrectangle for the dimension, determining if the data packet has reached the root node, and if the data packet has not reached the root node, routing the data packet among nodes along another dimension towards the root node.
摘要翻译：一种用于在多维计算机网络中路由数据分组的计算机实现的方法和系统。该方法包括沿着一个维度的节点之间的数据分组路由到根节点，每个节点具有输入和输出通信链路，所述根节点不具有任何输出上行链路，并且在每个节点处确定数据分组是否已经达到预定义的坐标尺寸或子尺寸的边缘，以及如果数据分组已达到尺寸的维度或边缘的尺寸的预定义坐标，则确定数据分组是否已到达根节点，并且如果数据分组数据包尚未到达根节点，将数据包沿着另一个维度的节点路由到根节点。

49. 发明授权

US08086766B2 Support for non-locking parallel reception of packets belonging to a single memory reception FIFO 有权
标题翻译：支持非锁定并行接收属于单个存储器接收FIFO的数据包
公开(公告)号：US08086766B2
公开(公告)日：2011-12-27
申请号：US12688747
申请日：2010-01-15
申请人： Dong Chen , Philip Heidelberger , Valentina Salapura , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Dong Chen , Philip Heidelberger , Valentina Salapura , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and apparatus for distributed parallel messaging in a parallel computing system. A plurality of DMA engine units are configured in a multiprocessor system to operate in parallel, one DMA engine unit for transferring a current packet received at a network reception queue to a memory location in a memory FIFO (rmFIFO) region of a memory. A control unit implements logic to determine whether any prior received packet destined for that rmFIFO is still in a process of being stored in the associated memory by another DMA engine unit of the plurality, and prevent the one DMA engine unit from indicating completion of storing the current received packet in the reception memory FIFO (rmFIFO) until all prior received packets destined for that rmFIFO are completely stored by the other DMA engine units. Thus, there is provided non-locking support so that multiple packets destined for a single rmFIFO are transferred and stored in parallel to predetermined locations in a memory.
摘要翻译：一种并行计算系统中分布式并行消息传递的方法和装置。多个DMA引擎单元被配置在多处理器系统中以并行操作，一个DMA引擎单元用于将在网络接收队列处接收的当前分组传送到存储器的存储器FIFO（rmFIFO）区域中的存储单元。控制单元实现逻辑以确定目的地为该rmFIFO的任何先前接收到的分组是否仍处于由多个的另一DMA引擎单元存储在相关联的存储器中的过程中，并且防止一个DMA引擎单元指示完成存储在接收存储器FIFO（rmFIFO）中的当前接收的分组直到所有先前接收到的该rmFIFO的分组被其它DMA引擎单元完全存储。因此，提供了非锁定支持，使得去往单个rmFIFO的多个分组被传送并存储在存储器中的预定位置。

50. 发明申请

US20110179199A1 SUPPORT FOR NON-LOCKING PARALLEL RECEPTION OF PACKETS BELONGING TO THE SAME RECEPTION FIFO 有权
标题翻译：支持非锁定并行接收与相同接收FIFO相关的分组
公开(公告)号：US20110179199A1
公开(公告)日：2011-07-21
申请号：US12688747
申请日：2010-01-15
申请人： Dong Chen , Philip Heidelberger , Valentina Salapura , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Dong Chen , Philip Heidelberger , Valentina Salapura , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and apparatus for distributed parallel messaging in a parallel computing system. A plurality of DMA engine units are configured in a multiprocessor system to operate in parallel, one DMA engine unit for transferring a current packet received at a network reception queue to a memory location in a memory FIFO (rmFIFO) region of a memory. A control unit implements logic to determine whether any prior received packet destined for that rmFIFO is still in a process of being stored in the associated memory by another DMA engine unit of the plurality, and prevent the one DMA engine unit from indicating completion of storing the current received packet in the reception memory FIFO (rmFIFO) until all prior received packets destined for that rmFIFO are completely stored by the other DMA engine units. Thus, there is provided non-blocking support so that multiple packets destined for a single rmFIFO are transferred and stored in parallel to predetermined locations in a memory.
摘要翻译：一种并行计算系统中分布式并行消息传递的方法和装置。多个DMA引擎单元被配置在多处理器系统中以并行操作，一个DMA引擎单元用于将在网络接收队列处接收的当前分组传送到存储器的存储器FIFO（rmFIFO）区域中的存储单元。控制单元实现逻辑以确定目的地为该rmFIFO的任何先前接收到的分组是否仍处于由多个的另一DMA引擎单元存储在相关联的存储器中的过程中，并且防止一个DMA引擎单元指示完成存储在接收存储器FIFO（rmFIFO）中的当前接收的分组直到所有先前接收到的该rmFIFO的分组被其它DMA引擎单元完全存储。因此，提供了非阻塞支持，使得目的地为单个rmFIFO的多个分组被传送并存储在存储器中的预定位置。

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