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41. 发明申请

US20100124102A1 Phase-Change and Resistance-Change Random Access Memory Devices and Related Methods of Performing Burst Mode Operations in Such Memory Devices 有权
标题翻译：相变和电阻变化随机存取存储器件以及在这种存储器件中执行突发模式操作的相关方法
公开(公告)号：US20100124102A1
公开(公告)日：2010-05-20
申请号：US12582880
申请日：2009-10-21
申请人： Kwang-Jin Lee , Young-kug Moon , Young-pil Kim
发明人： Kwang-Jin Lee , Young-kug Moon , Young-pil Kim
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/004 , G11C7/1018 , G11C8/18 , G11C11/5678 , G11C13/00 , G11C13/0004
摘要： Phase-change and resistance-change random access memory devices are provided which include a phase-change or resistance-change memory cell array and a sense amplifier that is configured to amplify data read from the phase-change memory cell array. These random access memory devices are configured to read data from a first word line of the phase-change or resistance-change memory cell array and to insert a dummy burst in which no data is read when a first boundary crossing occurs during a burst mode operation. Related methods of operating phase-change and/or resistance-change random access memory devices in burst mode are also provided.
摘要翻译：提供了相变和电阻变化随机存取存储器件，其包括相变或电阻变化存储单元阵列和被配置为放大从相变存储单元阵列读取的数据的读出放大器。这些随机存取存储器件被配置为从相变或电阻变化存储单元阵列的第一字线读取数据，并且在突发模式操作期间发生第一边界交叉时插入其中没有读取数据的虚拟脉冲串。还提供了以突发模式操作相变和/或电阻变化随机存取存储器件的相关方法。

42. 发明申请

US20090239348A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090239348A1
公开(公告)日：2009-09-24
申请号：US12478345
申请日：2009-06-04
申请人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
发明人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
IPC分类号： H01L21/336
CPC分类号： C30B29/06 , C30B15/00
摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.
摘要翻译：公开了一种形成在应变硅层上的半导体器件及其制造方法。根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

43. 发明申请

US20090008717A1 Semiconductor Devices Including Elevated Source and Drain Regions and Methods of Fabricating the Same 有权
标题翻译：包括提升源和排水区的半导体器件及其制造方法
公开(公告)号：US20090008717A1
公开(公告)日：2009-01-08
申请号：US12166575
申请日：2008-07-02
申请人： Jin-Bum Kim , Young-Pil Kim , Jung-Yun Won , Hion-Suck Baik , Jun-Ho Lee
发明人： Jin-Bum Kim , Young-Pil Kim , Jung-Yun Won , Hion-Suck Baik , Jun-Ho Lee
IPC分类号： H01L21/336 , H01L27/088
CPC分类号： H01L21/823456 , H01L21/823418 , H01L27/1052 , H01L27/10876 , H01L27/10894 , H01L29/4236 , H01L29/66621
摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.
摘要翻译：提供制造半导体器件的方法。制备具有活性图案和隔离层图案的基板。每个隔离层图案的上表面高于每个活动图案的上表面。在基板上形成具有均匀厚度的间隔层。蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。在每个有源图案上形成栅极结构。对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。还提供了相关的半导体器件。

44. 发明申请

US20080105930A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND RELATED FABRICATION METHOD 有权
标题翻译：半导体集成电路器件及相关制造方法
公开(公告)号：US20080105930A1
公开(公告)日：2008-05-08
申请号：US11855529
申请日：2007-09-14
申请人： Jin-bum KIM , Young-pil KIM , Si-young CHOI , Byeong-chan LEE , Jong-wook LEE
发明人： Jin-bum KIM , Young-pil KIM , Si-young CHOI , Byeong-chan LEE , Jong-wook LEE
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由隔离区。半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

45. 发明申请

US20080076676A1 Novel construction of gold nanoparticle-based peptide chip, and assaying enzyme activity and inhibitor effect using secondary ion mass spectrometric analysis thereof 有权
标题翻译：基于金纳米颗粒的肽芯片的新型构建，以及使用其二次离子质谱分析来测定酶活性和抑制剂效应
公开(公告)号：US20080076676A1
公开(公告)日：2008-03-27
申请号：US11711036
申请日：2007-02-27
申请人： Hak-Sung Kim , Young-Pil Kim , Eunkeu Oh , Mi-Young Hong , Dohoon Lee , Tae Lee , Dae Moon
发明人： Hak-Sung Kim , Young-Pil Kim , Eunkeu Oh , Mi-Young Hong , Dohoon Lee , Tae Lee , Dae Moon
IPC分类号： C40B30/10 , C12Q1/00 , C12Q1/37 , C40B40/10 , G01N33/68 , C12Q1/42 , C12Q1/48
CPC分类号： G01N33/6848 , B82Y15/00 , C12Q1/00 , C12Q1/37 , C12Q1/42 , C12Q1/485 , G01N33/553 , G01N33/588 , G01N2500/04 , G01N2610/00
摘要： Disclosed herein is a gold nanoparticle (AuNP)-based peptide chip prepared by forming a monolayer of AuNPs onto a self-assembled monolayer constructed on a solid support, and then immobilizing a peptide on the AuNPs. The AuNPs can effectively amplify the mass signal of the peptide, thus making it possible to measure the mass change of the peptide in a simple and accurate manner. Also, when secondary ion mass spectrometric analysis (spectrum or imaging) is performed on the AuNP-based peptide chip, the activities of enzymes and related inhibitors can be effectively quantified. The disclosed invention enables various enzyme activities to be analyzed rapidly and accurately, and thus can provide an important method for disease diagnosis and new drug development through the elucidation of signaling and interaction mechanisms.
摘要翻译：本文公开了通过在固体支持物上构建的自组装单层上形成单层AuNP，然后将肽固定在AuNP上而制备的金纳米颗粒（AuNP）基肽芯片。 AuNPs可以有效地扩增肽的质量信号，从而使得可以以简单和准确的方式测量肽的质量变化。此外，当在基于AuNP的肽芯片上进行二次离子质谱分析（光谱或成像）时，可以有效地量化酶和相关抑制剂的活性。所公开的发明使得能够快速且准确地分析各种酶活性，因此可以通过阐明信号和相互作用机制来提供疾病诊断和新药开发的重要方法。

46. 发明授权

US07323710B2 Fin field effect transistors having multi-layer fin patterns 失效
标题翻译：鳍场效应晶体管具有多层翅片图案
公开(公告)号：US07323710B2
公开(公告)日：2008-01-29
申请号：US10870743
申请日：2004-06-17
申请人： Young-Pil Kim , Sun-Ghil Lee , Si-Young Choi
发明人： Young-Pil Kim , Sun-Ghil Lee , Si-Young Choi
IPC分类号： H01L29/06 , H01L31/00
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： A fin field effect transistor has a fin pattern protruding from a semiconductor substrate. The fin pattern includes first semiconductor patterns and second semiconductor patterns which are stacked. The first and second semiconductor patterns have lattice widths that are greater than a lattice width of the substrate in at least one direction. In addition, the first and second semiconductor patterns may be alternately stacked to increase the height of the fin pattern, such that one of the first and second patterns can reduce stress from the other of the first and second patterns. The first and second semiconductor patterns may be formed of strained silicon and silicon-germanium, where the silicon-germanium patterns can reduce stress from the strained silicon patterns. Therefore, both the number of carriers and the mobility of carriers in the transistor channel may be increased, improving performance of the fin field effect transistor. Related methods are also discussed.
摘要翻译：鳍状场效应晶体管具有从半导体衬底突出的鳍状图案。鳍状图案包括堆叠的第一半导体图案和第二半导体图案。第一和第二半导体图案具有在至少一个方向上大于衬底的晶格宽度的晶格宽度。此外，第一和第二半导体图案可以交替堆叠以增加鳍片图案的高度，使得第一和第二图案中的一个可以减小来自第一和第二图案中的另一个的应力。第一和第二半导体图案可以由应变硅和硅 - 锗形成，其中硅 - 锗图案可以减小应变硅图案的应力。因此，可以增加晶体管沟道中的载流子数和载流子的迁移率，从而提高鳍式场效应晶体管的性能。还讨论了相关方法。

47. 发明授权

US07271408B2 Semiconductor device test patterns and related methods for precisely measuring leakage currents in semiconductor cell transistors 失效
标题翻译：用于精确测量半导体单元晶体管中的漏电流的半导体器件测试图案和相关方法
公开(公告)号：US07271408B2
公开(公告)日：2007-09-18
申请号：US10796672
申请日：2004-03-09
申请人： Young-pil Kim , Beom-jun Jin
发明人： Young-pil Kim , Beom-jun Jin
IPC分类号： H01L23/58
CPC分类号： H01L27/10882 , H01L22/32 , H01L27/108 , H01L27/10814 , H01L27/10894 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor device test patterns are provided that include a word line on a semiconductor substrate and an active region having a first impurity doped region and a second impurity doped region in at the semiconductor substrate. A first self-aligned contact pad is electrically connected to the first impurity doped region, and a first direct contact is electrically connected to the first self-aligned contact pad. A first bit line is electrically connected to the first direct contact, and a first probing pad is electrically connected to the first bit line. The test pattern further includes a second self-aligned contact pad that is electrically connected to the second impurity doped region, and a second direct contact electrically connected to the second self-aligned contact pad. A second conductive line is electrically connected to the second direct contact, and a second probing pad is electrically connected to the second conductive line. These test patterns may be used to measure leakage current in a cell transistor of the semiconductor device.
摘要翻译：提供半导体器件测试图案，其包括在半导体衬底上的字线和在半导体衬底中具有第一杂质掺杂区和第二杂质掺杂区的有源区。第一自对准接触焊盘电连接到第一杂质掺杂区域，第一直接接触电连接到第一自对准接触焊盘。第一位线电连接到第一直接触点，并且第一探针焊盘电连接到第一位线。测试图案还包括电连接到第二杂质掺杂区的第二自对准接触焊盘和电连接到第二自对准接触焊盘的第二直接接触。第二导电线电连接到第二直接接触，第二探测焊盘电连接到第二导线。这些测试图案可用于测量半导体器件的单元晶体管中的漏电流。

48. 发明授权

US06864178B1 Method of making a MOS transistor 有权
公开(公告)号：US06864178B1
公开(公告)日：2005-03-08
申请号：US10627059
申请日：2003-07-25
申请人： Young Pil Kim
发明人： Young Pil Kim
IPC分类号： H01L21/28 , H01L21/302 , H01L21/336 , H01L21/461 , H01L29/49 , H01L29/76
CPC分类号： H01L29/6653 , H01L21/28079 , H01L21/28097 , H01L29/495 , H01L29/665 , H01L29/66507 , H01L29/66545 , H01L29/6659
摘要： A method of making a MOS transistor is disclosed. The disclosed techniques can completely transform a polysilicon gate electrode into a metal silicide electrode through a brief thermal treatment process by extending the contact area between the polysilicide gate electrode and a metal layer prior to a formation of a metal silicide. The disclosed MOS transistor fabricating method comprises providing a semiconductor substrate further comprising a polysilicon gate electrode with a silicide layer thereon, a spacer, and source and drain regions with LDD regions; forming an insulating layer on the area of the substrate; polishing the insulating layer so that the top of the polysilicon gate electrode can be exposed; etching some part of the insulating layer and the spacer so that both lateral walls of the polysilicon gate electrode can be exposed; forming a metal layer on the substrate resulted from the preceding step so that the polysilicon gate electrode can be covered with the metal layer; and transforming completely the polysilicon gate electrode into a metal silicide gate electrode by performing a thermal treatment process.

49. 发明授权

US06858529B2 Methods of forming contact plugs including polysilicon doped with an impurity having a lesser diffusion coefficient than phosphorus 有权
标题翻译：形成接触塞的方法，包括掺杂有比磷更小的扩散系数的杂质的多晶硅
公开(公告)号：US06858529B2
公开(公告)日：2005-02-22
申请号：US10440777
申请日：2003-05-19
申请人： Eun-Ae Chung , Myoung-Bum Lee , Young-Pil Kim , Jin-Gyun Kim , Bean-Jun Jin
发明人： Eun-Ae Chung , Myoung-Bum Lee , Young-Pil Kim , Jin-Gyun Kim , Bean-Jun Jin
IPC分类号： H01L21/28 , H01L21/225 , H01L21/285 , H01L21/768 , H01L23/485 , H01L21/4763
CPC分类号： H01L21/76877 , H01L21/2257 , H01L21/28525 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.
摘要翻译：形成半导体器件可以包括在包括其导电区域的半导体衬底上形成绝缘层，其中绝缘层具有暴露导电区域的一部分的接触孔。可以在接触孔中形成多晶硅接触插塞，其中多晶硅接触插塞的至少一部分掺杂有具有小于磷（P）的扩散系数的扩散系数的元件。还讨论了相关结构。

50. 发明授权

US08853010B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08853010B2
公开(公告)日：2014-10-07
申请号：US13368584
申请日：2012-02-08
申请人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
发明人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336 , H01L21/337 , H01L21/338 , H01L21/339 , H01L29/165 , H01L29/78 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/1608 , H01L29/165 , H01L29/66545 , H01L29/66621 , H01L29/66651 , H01L29/78
摘要： A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.
摘要翻译：半导体器件包括衬底和在衬底上彼此间隔开的第一和第二应力产生外延区域。沟道区位于衬底上并位于第一和第二应力产生外延区之间。栅电极在沟道区上。沟道区域是外延层，并且第一和第二应力产生外延区域对沟道区域施加应力。

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