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41. 发明授权

US5950098A Manufacturing method of a semiconductor device with a silicide layer 失效
标题翻译：具有硅化物层的半导体器件的制造方法
公开(公告)号：US5950098A
公开(公告)日：1999-09-07
申请号：US911979
申请日：1997-08-15
申请人： Hidekazu Oda , Takashi Kuroi
发明人： Hidekazu Oda , Takashi Kuroi
IPC分类号： H01L29/78 , H01L21/265 , H01L21/28 , H01L21/285 , H01L21/336 , H01L29/45 , H01L29/49 , H01L21/425
CPC分类号： H01L29/66575 , H01L21/28052 , H01L21/28518 , H01L29/456 , H01L29/4933
摘要： To form a silicide layer excellent in flatness, uniform in film thickness, and less in junction leak, by destroying the natural oxide film which adversely affects a formation of silicide layer of cobalt or nickel. A cobalt layer (7) is formed in a film thickness of 20 nm or less on an electrode layer (4A) of a gate electrode (4) and on source/drain diffusion layers (1, 2), and a nitrogen (8) is injected by the ion implantation at a density of about 1E15/cm.sup.3 with an injection energy of 10 keV or more. At this time, the nitrogens (8) destroy the natural oxide film existing in the interface of the cobalt layer (7) and electrode layer (4A), and in the interface of the cobalt layer (7) and the source/drain diffusion layers (1, 2), and distribute deeply into the electrode layer (4A) and the source/drain diffusion layers (1, 2). Later, by a silicide forming reaction of cobalt, a silicide layer (6) is formed. Since the natural oxide film does not exist, the silicide forming reaction proceeds uniformly. Instead of the nitrogen (8), fluorine or silicon may be also used.
摘要翻译：通过破坏对钴或镍的硅化物层的形成有不利影响的自然氧化膜，形成平坦度优异，膜厚均匀，并且漏点较少的硅化物层。在栅电极（4）的电极层（4A）和源/漏扩散层（1,2）上形成厚度为20nm以下的钴层（7），氮（8）通过离子注入以约1E15 / cm3的密度注入，注入能量为10keV以上。此时，氮（8）破坏存在于钴层（7）和电极层（4A）的界面中的自然氧化膜，并且在钴层（7）和源极/漏极扩散层（1,2），并且深深地分布到电极层（4A）和源极/漏极扩散层（1,2）中。然后，通过钴的硅化物形成反应，形成硅化物层（6）。由于天然氧化物膜不存在，所以硅化物形成反应均匀地进行。代替氮（8），也可以使用氟或硅。

42. 发明授权

US5932912A Semiconductor device having LDD structure with a recess in the source/drain region which is formed during the removal of a damaged layer 失效
标题翻译：具有LDD结构的半导体器件在源极/漏极区域中具有在去除损坏层期间形成的凹部
公开(公告)号：US5932912A
公开(公告)日：1999-08-03
申请号：US946390
申请日：1997-10-07
申请人： Katsuyuki Horita , Takashi Kuroi , Yoshinori Okumura
发明人： Katsuyuki Horita , Takashi Kuroi , Yoshinori Okumura
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L27/108 , H01L29/06 , H01L29/76 , H01L29/78
CPC分类号： H01L21/76814 , H01L27/1052 , H01L27/10873 , H01L29/0847 , H01L29/6659 , H01L29/66636 , H01L29/66659 , H01L29/7834 , H01L29/7835 , H01L27/108 , H01L27/10885 , H01L27/11 , H01L27/1104
摘要： To obtain a semiconductor device which prevents an increase in the resistance of a source/drain region; which operates fast and stably; and which provides a high manufacturing yield, and to obtain a method of manufacturing the semiconductor device. A recess 8 is formed on a first low impurity-concentration region 5 with the exception of the area immediately below side wall insulating material 6y, and a layer damaged as a result of formation of the side wall insulating material 6y is removed. Further, a second low impurity-concentration region 10 is formed below the recess 8.
摘要翻译：获得防止源极/漏极区域的电阻增加的半导体器件; 运行快速稳定; 并且其提供高的制造成品率，并且获得制造半导体器件的方法。除了紧邻侧壁绝缘材料6y的区域之外，在第一低杂质浓度区域5上形成凹部8，并且除去由于形成侧壁绝缘材料6y而损坏的层。此外，在凹部8的下方形成第二低杂质浓度区域10。

43. 发明授权

US06841440B2 Semiconductor device including impurity layer having continuous portions formed at different depths and method of manufacturing the same 有权
标题翻译：包括具有在不同深度形成的连续部分的杂质层的半导体器件及其制造方法
公开(公告)号：US06841440B2
公开(公告)日：2005-01-11
申请号：US10352097
申请日：2003-01-28
申请人： Takashi Kuroi , Syuichi Ueno , Katsuyuki Horita
发明人： Takashi Kuroi , Syuichi Ueno , Katsuyuki Horita
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/10 , H01L29/78
CPC分类号： H01L21/823481 , H01L21/76235 , H01L29/1033
摘要： A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N+-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.
摘要翻译：在衬底中形成沟槽，并且用作沟槽隔离的氧化硅膜被埋在沟槽中。氧化硅膜没有从基板的主表面下垂的形状。在基板的主表面上形成用于控制MOSFET的阈值电压的沟道杂质层。沟道杂质层由P型层构成，其杂质浓度高于衬底的杂质浓度。沟道杂质层的第一部分沿沟槽的开口边缘形成在源极/漏极层中的沟槽的侧表面附近，更具体地，形成在N +型层中。沟道杂质层的第二部分形成得比第一部分更深。栅极绝缘膜和栅电极形成在基板的主表面上。

44. 发明授权

US06667221B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06667221B2
公开(公告)日：2003-12-23
申请号：US10212274
申请日：2002-08-06
申请人： Masashi Kitazawa , Tomohiro Yamashita , Takashi Kuroi
发明人： Masashi Kitazawa , Tomohiro Yamashita , Takashi Kuroi
IPC分类号： H01L2176
CPC分类号： H01L23/544 , H01L21/3081 , H01L21/76229 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A technique for preventing a decrease in alignment accuracy during a photolithography process is provided. A substrate (1) is prepared, in the surface (80) of which trenches (7) for use as alignment marks and trenches (17, 27) each forming an element isolation structure are formed and on the surface (80) of which a polysilicon film (3) is formed, avoiding the trenches (7, 17, 27). The trenches (7, 17, 27) are filled with an insulation film (30). The insulation film (30) is then selectively etched to partially remove the insulation film (30) in the trenches (7) and to leave the insulation film (30) on side and bottom surfaces (81, 82) of the trenches (7). Using the insulation film (30) in the trenches (7) as a protective film, the polysilicon film (3) is selectively etched. The use of the insulation film (30) in the trenches (7) as a protective film prevents the substrate (1) from being etched and thereby prevents the shape of the trenches (7) from being changed. This results in prevention of a decrease in alignment accuracy during a photolithography process.
摘要翻译：提供了一种在光刻工艺中防止对准精度降低的技术。在表面（80）中制备基板（1），其中形成用作对准标记的沟槽（7）和形成元件隔离结构的沟槽（17,27），并且其表面（80）形成多晶硅膜（3），避免了沟槽（7,17,27）。沟槽（7,17,27）填充绝缘膜（30）。然后选择性地蚀刻绝缘膜（30）以部分去除沟槽（7）中的绝缘膜（30）并且在沟槽（7）的侧面和底面（81,82）上留下绝缘膜（30）。使用沟槽（7）中的绝缘膜（30）作为保护膜，选择性地蚀刻多晶硅膜（3）。使用作为保护膜的沟槽（7）中的绝缘膜（30）可防止基板（1）被蚀刻，从而防止沟槽（7）的形状发生变化。这导致防止在光刻工艺期间对准精度降低。

45. 发明授权

US06577021B2 Static-type semiconductor memory device 失效
公开(公告)号：US06577021B2
公开(公告)日：2003-06-10
申请号：US10096728
申请日：2002-03-14
申请人： Chikayoshi Morishima , Yoshinori Okumura , Takashi Kuroi
发明人： Chikayoshi Morishima , Yoshinori Okumura , Takashi Kuroi
IPC分类号： H01L2711
CPC分类号： H01L27/1104 , Y10S257/904
摘要： An SRAM of the present invention comprises a plurality of memory cells, which are formed over a plurality of wells, which store data and which do not have a well contact region for fixing the potential of the wells, and a plurality of well contact cells for fixing the potential of the wells that are formed over the plurality of wells so as to adjoin the memory cells, wherein the areas of the memory cells and the areas of the well contact cells are equal.

46. 发明授权

US06541825B2 Semiconductor device including impurity layer having continuous portions formed at different depths and method of manufacturing the same 有权
标题翻译：包括具有在不同深度形成的连续部分的杂质层的半导体器件及其制造方法
公开(公告)号：US06541825B2
公开(公告)日：2003-04-01
申请号：US09805923
申请日：2001-03-15
申请人： Takashi Kuroi , Syuichi Ueno , Katsuyuki Horita
发明人： Takashi Kuroi , Syuichi Ueno , Katsuyuki Horita
IPC分类号： H01L2976
CPC分类号： H01L21/823481 , H01L21/76235 , H01L29/1033
摘要： A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N+-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.
摘要翻译：在衬底中形成沟槽，并且用作沟槽隔离的氧化硅膜被埋在沟槽中。氧化硅膜没有从基板的主表面下垂的形状。在基板的主表面上形成用于控制MOSFET的阈值电压的沟道杂质层。沟道杂质层由P型层构成，其杂质浓度高于衬底的杂质浓度。沟道杂质层的第一部分沿着沟槽的开口边缘形成在源极/漏极层中的沟槽的侧表面附近，更具体地，形成在N +型层中。沟道杂质层的第二部分形成得比第一部分更深。栅极绝缘膜和栅电极形成在基板的主表面上。

47. 发明授权

US06503799B2 Method of manufacturing semiconductor device 失效
公开(公告)号：US06503799B2
公开(公告)日：2003-01-07
申请号：US09991959
申请日：2001-11-26
申请人： Katsuyuki Horita , Takashi Kuroi , Shuuichi Ueno
发明人： Katsuyuki Horita , Takashi Kuroi , Shuuichi Ueno
IPC分类号： H01L21205
CPC分类号： H01L21/76264 , H01L21/76272
摘要： There is provided a method of forming an element isolation structure that can maintain its element isolation capability even with the progress of miniaturization of semiconductor elements. Through thermal processing in a nitrogen atmosphere at 900° C., a non single-crystal silicon film (80) is crystallized into single-crystal form by epitaxial growth on the main surface of a substrate, thereby to form an epitaxial silicon film (85). The epitaxial silicon film (85) is then planarized by CMP to expose the upper surface of an element isolation insulating film (50). This completes the element isolation insulating film (50) having a two-level protruding shape.

48. 发明授权

US06383884B1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06383884B1
公开(公告)日：2002-05-07
申请号：US09496057
申请日：2000-02-02
申请人： Katsuomi Shiozawa , Takashi Kuroi , Yasuyoshi Itoh , Katsuyuki Horita
发明人： Katsuomi Shiozawa , Takashi Kuroi , Yasuyoshi Itoh , Katsuyuki Horita
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/28247 , H01L29/66537
摘要： A semiconductor device includes a silicon substrate (1), a pair of isolating insulation films (9), a channel region (2), a pair of source/drain regions (3), a pair of silicon oxide films (4) formed on an upper surface of the silicon substrate (1) so as to overlie the source/drain regions (3), and a gate structure (8) formed in a first recess defined by the upper surface of the silicon substrate (1) over the channel region (2) and side surfaces of the pair of silicon oxide films (4). The gate structure (8) includes a gate oxide film (5) formed on the upper surface of the silicon substrate (1), a pair of silicon oxide films (6) formed on lower part of the side surfaces of the pair of silicon oxide films (4), and a metal film (7) filling a second recess surrounded by upper part of the side surfaces of the silicon oxide films (4), the silicon oxide films (6) and the gate oxide film (5). A method of manufacturing the semiconductor device is provided which attains reduction in gate length without the decrease in driving capability to accomplish the increase in operating speed.
摘要翻译：半导体器件包括硅衬底（1），一对隔离绝缘膜（9），沟道区（2），一对源/漏区（3），一对氧化硅膜（4），形成在硅衬底（1）的上表面覆盖在源极/漏极区（3）上，并且栅极结构（8）形成在由硅衬底（1）的上表面限定的第一凹部中，沟道区域（2）和一对氧化硅膜（4）的侧表面。栅极结构（8）包括形成在硅衬底（1）的上表面上的栅氧化膜（5），一对氧化硅膜（6），形成在该一对氧化硅的侧表面的下部以及填充由氧化硅膜（4）的侧面的上部，氧化硅膜（6）和栅极氧化膜（5）所包围的第二凹部的金属膜（7）。提供了一种制造半导体器件的方法，其在不降低驱动能力的情况下实现栅极长度的减小以实现操作速度的提高。

49. 发明授权

US06300664B1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06300664B1
公开(公告)日：2001-10-09
申请号：US08880508
申请日：1997-06-23
申请人： Takashi Kuroi , Shuichi Ueno , Hidekazu Oda , Satoshi Shimizu
发明人： Takashi Kuroi , Shuichi Ueno , Hidekazu Oda , Satoshi Shimizu
IPC分类号： H01L2976
CPC分类号： H01L29/0847 , H01L21/28176 , H01L21/28202 , H01L21/823857 , H01L29/4908 , H01L29/4916 , H01L29/4933 , H01L29/51 , H01L29/518 , H01L29/665 , H01L29/66575 , H01L29/6659 , H01L29/66765 , H01L29/7833 , H01L29/78618
摘要： Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P+-type gate electrode which are formed on a P-type silicon substrate are doped with nitrogen.
摘要翻译：获得的是能够防止栅电极中所含杂质扩散的半导体器件及其制造方法。在该半导体器件中，形成在P型硅衬底上的栅极氧化膜和P +型栅极掺杂有氮。

50. 发明授权

US06268263B1 Method of forming a trench type element isolation in semiconductor substrate 失效
标题翻译：在半导体衬底中形成沟槽型元件隔离的方法
公开(公告)号：US06268263B1
公开(公告)日：2001-07-31
申请号：US09196134
申请日：1998-11-20
申请人： Maiko Sakai , Takashi Kuroi , Katsuyuki Horita
发明人： Maiko Sakai , Takashi Kuroi , Katsuyuki Horita
IPC分类号： H01L2176
CPC分类号： H01L21/31053 , H01L21/76224 , Y10S438/97
摘要： A trench (21) is formed in a silicon substrate (1) on which an underlying oxide film (2) and a silicon nitride film (3) are formed. Then, a silicon oxide (11) is deposited by an HDP-CVD method to fill the trench (21) with the oxide. Further, a resist (41) including a second resist portion (42), and a resist (43) are formed. The silicon oxide film (11) that is not covered with the resists (41) and (43), is removed by dry etching. Etch selectivity of the silicon oxide film (11) to the stopper film (3) is not less than a value (2(c−a)/d) obtained by dividing twice a value (c−a) which is obtained by subtracting an alignment margin (a) from the maximum film thickness (c) of the silicon oxide film (11), by the film thickness (d) of the stopper film (3). The resists (41) and (43) are then removed, and the residual silicon oxide film (11B, 11DC, 11DE, 11FE) is polished and removed by the CMP method. This forms a trench type element isolation with no depression at its edge portion.
摘要翻译：在其上形成有下面的氧化膜（2）和氮化硅膜（3）的硅衬底（1）中形成沟槽（21）。然后，通过HDP-CVD法沉积氧化硅（11）以用氧化物填充沟槽（21）。此外，形成包括第二抗蚀剂部分（42）和抗蚀剂（43）的抗蚀剂（41）。通过干蚀刻除去未被抗蚀剂（41）和（43）覆盖的氧化硅膜（11）。氧化硅膜（11）对阻挡膜（3）的蚀刻选择性不小于通过将通过减去取向余量（a）获得的值（ca）的两倍所获得的值（2（ca）/ d））从氧化硅膜（11）的最大膜厚度（c）到阻挡膜（3）的膜厚度（d）。然后除去抗蚀剂（41）和（43），并通过CMP方法研磨和除去残留氧化硅膜（11B，11DC，11DE，11FE）。这形成了在其边缘部分没有凹陷的沟槽型元件隔离。

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