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41. 发明授权

US6104078A Design for a semiconductor device having elements isolated by insulating regions 失效
标题翻译：设计具有通过绝缘区隔离的元件的半导体器件
公开(公告)号：US6104078A
公开(公告)日：2000-08-15
申请号：US941756
申请日：1997-09-30
申请人： Makio Iida , Mitsuhiro Saitou , Akitaka Murata , Hiroyuki Ban , Tadashi Suzuki , Toshio Sakakibara , Takayuki Sugisaka , Shoji Miura
发明人： Makio Iida , Mitsuhiro Saitou , Akitaka Murata , Hiroyuki Ban , Tadashi Suzuki , Toshio Sakakibara , Takayuki Sugisaka , Shoji Miura
IPC分类号： H01L21/762 , H01L29/36
CPC分类号： H01L21/76264
摘要： A semiconductor device including a semiconductor substrate having a main surface. An insulating film is formed on the main surface of the semiconductor substrate. A semiconductor layer is placed on the insulating film. Side insulating regions extending from a surface of the semiconductor layer to the insulating film divide the semiconductor layer into element regions. The element regions are isolated from each other by the side insulating regions and the insulating film. The semiconductor substrate has a resistivity of 1.5 .OMEGA.cm or lower. A voltage at the semiconductor substrate is set to a given voltage.
摘要翻译：一种半导体器件，包括具有主表面的半导体衬底。绝缘膜形成在半导体衬底的主表面上。半导体层被放置在绝缘膜上。从半导体层的表面延伸到绝缘膜的侧绝缘区域将半导体层分成元件区域。元件区域通过侧绝缘区域和绝缘膜彼此隔离。半导体基板的电阻率为1.5欧姆·厘米或更低。将半导体衬底处的电压设定为给定电压。

42. 发明授权

US5599722A SOI semiconductor device and method of producing same wherein warpage is reduced in the semiconductor device 失效
标题翻译： SOI半导体器件及其制造方法，其中在半导体器件中翘曲减小
公开(公告)号：US5599722A
公开(公告)日：1997-02-04
申请号：US346255
申请日：1994-11-23
申请人： Takayuki Sugisaka , Shoji Miura , Toshio Sakakibara
发明人： Takayuki Sugisaka , Shoji Miura , Toshio Sakakibara
IPC分类号： H01L21/02 , H01L21/76 , H01L21/762 , H01L27/12 , H01L21/265 , H01L21/302
CPC分类号： H01L21/76264 , H01L21/76275 , H01L21/76281 , H01L21/76286
摘要： A trench isolation junction type SOI semiconductor device which reduces substrate warpage while suppressing increase in production steps and a method for producing the same are disclosed. A junction substrate is formed by bonding a semiconductor substrate having an outer insulation film on a non-junction main surface with a semiconductor layer with an inner insulation film sandwiched therebetween. After forming a silicon nitride film as a mask for the purpose of forming a trench in the semiconductor layer, silicon nitride film accumulated on the outer insulation film is removed. By doing this, warpage of the semiconductor substrate due to discrepancies in the thermal expansion rates of the rigid silicon nitride film and semiconductor substrate can be prevented. In a junction type SOI semiconductor device formed via the method, an outer insulation film of identical thickness and identical density to an inner insulation film is formed on a non-junction main surface (i.e., rear surface) of a semiconductor substrate. By doing this, warpage of the semiconductor substrate can be prevented.
摘要翻译：公开了一种在抑制生产步骤增加的同时降低衬底翘曲的沟槽隔离结型SOI半导体器件及其制造方法。通过在非接合主表面上具有外绝缘膜的半导体衬底与夹在其间的内绝缘膜的半导体层结合来形成接合衬底。在形成用于在半导体层中形成沟槽的掩模的氮化硅膜之后，除去积聚在外绝缘膜上的氮化硅膜。通过这样做，可以防止由于刚性氮化硅膜和半导体衬底的热膨胀率的差异导致的半导体衬底的翘曲。在通过该方法形成的结型SOI半导体器件中，在半导体衬底的非接合主表面（即后表面）上形成具有相同厚度和与内绝缘膜相同密度的外绝缘膜。通过这样做，可以防止半导体衬底的翘曲。

43. 发明授权

US5592015A Dielectric isolated type semiconductor device provided with bipolar element 失效
标题翻译：具有双极元件的绝缘隔离型半导体器件
公开(公告)号：US5592015A
公开(公告)日：1997-01-07
申请号：US547740
申请日：1995-10-26
申请人： Makio Iida , Tadashi Shibata , Takayuki Sugisaka , Shoji Miura , Toshio Sakakibara
发明人： Makio Iida , Tadashi Shibata , Takayuki Sugisaka , Shoji Miura , Toshio Sakakibara
IPC分类号： H01L29/73 , H01L21/331 , H01L21/762 , H01L21/763 , H01L27/02 , H01L29/732 , H01L29/00 , H01L23/58
CPC分类号： H01L29/7322 , H01L21/76264 , H01L21/763 , H01L27/0248 , H01L21/76286
摘要： A semiconductor device is provided which makes a high withstand voltage bipolar transistor small and prevents deterioration in a switching speed of the transistor. A silicon oxide layer is formed on a silicon substrate, and a semiconductor island of one conductivity type which is isolated laterally by an isolation trench is formed on the silicon oxide layer. A silicon oxide film is formed on an outer periphery portion of the semiconductor island to bury the trench. In the semiconductor island, a bipolar transistor, namely a base region of the other conductivity type, is formed, and in the base region an emitter region of one conductivity type is formed and a collector region of one conductivity type is further formed. In the semiconductor island a diffusion region of the other conductivity type for extracting excessive carriers to which a constant electric potential is applied is further formed.
摘要翻译：提供一种半导体器件，其使得高耐压双极晶体管变小，并防止晶体管的开关速度的劣化。在硅衬底上形成硅氧化物层，在氧化硅层上形成由隔离沟侧向隔离的一种导电型半导体岛。在半导体岛的外周部形成有氧化硅膜，以埋置沟槽。在半导体岛中，形成双极晶体管，即另一种导电型的基极区域，在基极区域形成一个导电型的发射极区域，并进一步形成一种导电型的集电极区域。在半导体岛中，进一步形成用于提取施加恒定电位的过量载流子的另一导电类型的扩散区域。

44. 发明授权

US5557134A Dielectric isolated type semiconductor device 失效
标题翻译：绝缘隔离型半导体器件
公开(公告)号：US5557134A
公开(公告)日：1996-09-17
申请号：US341977
申请日：1994-11-16
申请人： Takayuki Sugisaka , Toshio Sakakibara , Shoji Miura , Makio Iida
发明人： Takayuki Sugisaka , Toshio Sakakibara , Shoji Miura , Makio Iida
IPC分类号： H01L21/322 , H01L21/331 , H01L21/76 , H01L21/762 , H01L21/763 , H01L29/73 , H01L29/732 , H01L29/866 , H01L29/00
CPC分类号： H01L21/76264 , H01L21/3226 , H01L21/763 , H01L29/7317 , H01L29/732 , H01L21/76275 , H01L21/76286
摘要： A dielectric isolated type semiconductor device which can achieve a reduction in crystalline defects by means of a simple production process is provided. High-concentration regions are formed as active regions on a surface portion of an islandish semiconductor region which is isolated from an adjacent semiconductor region by means of an isolation trench. According to a first aspect of the present invention, an N type crystalline defect suppression region doped at a high concentration and deeper than the high-concentration regions is formed over the entire surface of an adjacent semiconductor region. According to a second aspect of the present invention, a high-concentration N type crystalline defect suppression region is provided on a surface portion of a P type high-concentration region is formed with identical structure and by an identical production process. By means of these N type regions, crystalline defects are reduced.
摘要翻译：提供了一种能够通过简单的制造工艺实现结晶缺陷降低的绝缘隔离型半导体器件。在通过隔离沟槽与相邻的半导体区域隔离的岛状半导体区域的表面部分上形成高浓度区域作为有源区域。根据本发明的第一方面，在相邻的半导体区域的整个表面上形成了在高浓度区域和高浓度区域掺杂的N型晶体缺陷抑制区域。根据本发明的第二方面，在P型高浓度区域的表面部分上形成高浓度的N型结晶缺陷抑制区域，其结构相同，生产方法相同。通过这些N型区域，晶体缺陷减少。

45. 发明授权

US5423941A Dry etching process for semiconductor 失效
标题翻译：半导体干蚀刻工艺
公开(公告)号：US5423941A
公开(公告)日：1995-06-13
申请号：US152896
申请日：1993-11-17
申请人： Atsushi Komura , Yoshikazu Sakano , Kenji Kondo , Keiichi Kon , Tetsuhiko Sanbei , Shoji Miura
发明人： Atsushi Komura , Yoshikazu Sakano , Kenji Kondo , Keiichi Kon , Tetsuhiko Sanbei , Shoji Miura
IPC分类号： H01L21/302 , H01L21/3065 , C23F1/00
CPC分类号： H01L21/3065
摘要： A process for forming deep trenches on a surface of a semiconductor substrate by forming a mask on the surface of the semiconductor, which prescribes the position of the trenches; and then dry etching the semiconductor surface using a gas mixture comprising (1) an etchant, bromine containing, gas which etches the semiconductor surface to form trenches, (2) a cleaning, halogen containing, gas which evaporates the residue formed by the etching; and (3) a reactive gas capable of reacting with material formed during the etching and capable of decreasing the wastage of the mask by the etchant gas.
摘要翻译：一种通过在半导体的表面上形成掩模来形成半导体衬底的表面上的深沟槽的方法，其规定了沟槽的位置; 然后使用气体混合物干燥蚀刻半导体表面，所述气体混合物包括（1）蚀刻剂，含溴的气体，蚀刻半导体表面以形成沟槽，（2）清洁，含卤素的气体，其蒸发由蚀刻形成的残余物; 和（3）能够与在蚀刻期间形成的材料反应的反应气体，并且能够通过蚀刻剂气体减少掩模的浪费。

46. 发明授权

US5284794A Method of making semiconductor device using a trimmable thin-film resistor 失效
标题翻译：使用可调薄膜电阻制造半导体器件的方法
公开(公告)号：US5284794A
公开(公告)日：1994-02-08
申请号：US960298
申请日：1992-10-13
申请人： Yoshihiko Isobe , Makio Iida , Shoji Miura , Keizou Kajiura , Mikimasa Suzuki , Masami Saito
发明人： Yoshihiko Isobe , Makio Iida , Shoji Miura , Keizou Kajiura , Mikimasa Suzuki , Masami Saito
IPC分类号： H01L21/02 , H01L21/26
CPC分类号： H01L28/24 , H01L28/40 , Y10S148/055 , Y10S148/136 , Y10S438/94
摘要： A semiconductor device has a thin-film resistor trimmed by laser. The semiconductor device comprises a semiconductor substrate having an element region that covers at least part of the surface of the semiconductor substrate, a first insulation film disposed on the surface of the semiconductor substrate, and a second insulation film disposed on the surface of the semiconductor substrate through an opening of the first insulation film. The opening is formed by selectively removing at least part of the first insulation film at a location on the surface of the semiconductor substrate where the element region is not involved. The thin-film resistor is formed on the second insulation film.
摘要翻译：半导体器件具有通过激光器修整的薄膜电阻器。半导体器件包括具有覆盖半导体衬底的表面的至少一部分的元件区域的半导体衬底，设置在半导体衬底的表面上的第一绝缘膜和设置在半导体衬底的表面上的第二绝缘膜通过第一绝缘膜的开口。通过在不涉及元件区域的半导体衬底的表面上的位置处选择性地去除第一绝缘膜的至少一部分来形成开口。薄膜电阻器形成在第二绝缘膜上。

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