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41. 发明授权

US08054370B2 Wiring substrate, solid-state imaging apparatus using the same, and manufacturing method thereof 失效
标题翻译：接线基板，使用其的固态成像装置及其制造方法
公开(公告)号：US08054370B2
公开(公告)日：2011-11-08
申请号：US12650610
申请日：2009-12-31
申请人： Min-Kyo Cho , Jae-Cheon Doh , Young-Shin Kwon
发明人： Min-Kyo Cho , Jae-Cheon Doh , Young-Shin Kwon
IPC分类号： H04N5/225
CPC分类号： H04N5/2251 , H01L27/14618 , H01L27/14806 , H01L31/0203 , H01L31/02325 , H01L2224/49171 , H04N5/2253 , H04N5/2254 , H01L2224/48091 , H01L2924/00014
摘要： In one embodiment, a miniaturized solid-state imaging apparatus includes a body having a cavity for mounting a semiconductor chip therein. The body has an overhanging portion extending toward the cavity. Further, a lead is disposed within the body. The lead has one end exposed through a top surface of the body and the other end exposed through a bottom surface of the body for electrical connection thereof.
摘要翻译：在一个实施例中，小型化固态成像装置包括具有用于将半导体芯片安装在其中的空腔的主体。主体具有向空腔延伸的伸出部分。此外，引线设置在身体内。引线的一端通过主体的顶表面暴露，而另一端通过主体的底表面暴露以与其电连接。

42. 发明授权

US07696048B2 Method of improving gate resistance in a memory array 失效
标题翻译：提高存储器阵列中栅极电阻的方法
公开(公告)号：US07696048B2
公开(公告)日：2010-04-13
申请号：US11425065
申请日：2006-06-19
申请人： Hyung-Shin Kwon , Seug-Gyu Kim
发明人： Hyung-Shin Kwon , Seug-Gyu Kim
IPC分类号： H01L21/8232 , H01L21/8239
CPC分类号： H01L21/823468 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L27/1116
摘要： A semiconductor device is formed with a normal, non-recessed, spacer structure in a cell region and a recessed spacer structure in a peripheral region. The recessed spacer structure is formed as by etch masking those in the cell region and exposing those in the peripheral region, then performing an etch process. The increased height of the cell region spacers is adapted to further prevent over-etching during gate interconnect formation which would otherwise result in etching through the spacer to the substrate and subsequent short circuit. Therefore, it is also possible to prevent bridge defects due to over-etching, which occurs because the barrier metal layer for a subsequent interconnection contact is accidentally connected to the underlying substrate. Also, since the recessed spacer structure is provided in the peripheral region, it is possible to remarkably enhance a resistance distribution of a cobalt silicide layer occurring in a gate line width of 100 nm or less.
摘要翻译：半导体器件在单元区域中具有正常的非凹入的间隔结构，并且在周边区域中形成有凹入的间隔结构。凹陷的间隔结构通过蚀刻掩蔽细胞区域中的那些并且暴露在外围区域中的那些，然后进行蚀刻工艺而形成。单元区域间隔物的增加的高度适于进一步防止在栅极互连形成期间的过度蚀刻，否则将导致通过间隔物蚀刻到衬底和随后的短路。因此，也可以防止由于用于随后的互连接触的阻挡金属层意外地连接到下面的基板而发生的由于过蚀刻而引起的桥接缺陷。此外，由于在周边区域设置凹陷的间隔结构，因此可以显着提高出现在100nm以下的栅极线宽度的硅化钴层的电阻分布。

43. 发明授权

US07659936B2 Wiring substrate, solid-state imaging apparatus using the same, and manufacturing method thereof 失效
标题翻译：接线基板，使用其的固态成像装置及其制造方法
公开(公告)号：US07659936B2
公开(公告)日：2010-02-09
申请号：US11053209
申请日：2005-02-07
申请人： Min-Kyo Cho , Jae-Cheon Doh , Young-Shin Kwon
发明人： Min-Kyo Cho , Jae-Cheon Doh , Young-Shin Kwon
IPC分类号： H04N5/225
CPC分类号： H04N5/2251 , H01L27/14618 , H01L27/14806 , H01L31/0203 , H01L31/02325 , H01L2224/49171 , H04N5/2253 , H04N5/2254 , H01L2224/48091 , H01L2924/00014
摘要： In one embodiment, a miniaturized solid-state imaging apparatus includes a body having a cavity for mounting a semiconductor chip therein. The body has an overhanging portion extending toward the cavity. Further, a lead is disposed within the body. The lead has one end exposed through a top surface of the body and the other end exposed through a bottom surface of the body for electrical connection thereof.
摘要翻译：在一个实施例中，小型化固态成像装置包括具有用于将半导体芯片安装在其中的空腔的主体。主体具有向空腔延伸的伸出部分。此外，引线设置在身体内。引线的一端通过主体的顶表面暴露，而另一端通过主体的底表面暴露以与其电连接。

44. 发明授权

US07405760B2 Image pickup device with non-molded DSP chip and manufacturing method 有权
标题翻译：具有非模制DSP芯片的图像拾取器件及其制造方法
公开(公告)号：US07405760B2
公开(公告)日：2008-07-29
申请号：US10347184
申请日：2003-01-21
申请人： Min Kyo Cho , Sa Yoon Kang , Young Hoon Ro , Young Shin Kwon
发明人： Min Kyo Cho , Sa Yoon Kang , Young Hoon Ro , Young Shin Kwon
IPC分类号： H04N5/225
CPC分类号： H04N5/2253 , H01L2224/32145 , H01L2224/48091 , H01L2224/92247 , H01L2924/00014
摘要： An image pickup device and a manufacturing method thereof. A digital signal processing (DSP) chip is attached on a first surface of a substrate. A CMOS image sensor (CIS) chip is attached on an active surface of the DSP chip. The DSP chip and the CIS chip may be electrically connected to the substrate by wire bonding. A housing kit having a lens configured to transmit an image to the DSP chip may be mounted on the substrate. An inner space between the housing kit and the substrate is not molded, thereby simplifying a manufacturing process and providing a thinner and/or lighter image pickup device.
摘要翻译：一种摄像装置及其制造方法。数字信号处理（DSP）芯片附着在基板的第一表面上。 CMOS图像传感器（CIS）芯片附着在DSP芯片的有源表面上。 DSP芯片和CIS芯片可以通过引线接合电连接到基板。具有被配置为将图像传送到DSP芯片的透镜的外壳套件可以安装在基板上。外壳套件和基板之间的内部空间不被模制，从而简化制造过程并提供更薄和/或更轻的图像拾取装置。

45. 发明授权

US07385260B2 Semiconductor device having silicide thin film and method of forming the same 有权
标题翻译：具有硅化物薄膜的半导体器件及其形成方法
公开(公告)号：US07385260B2
公开(公告)日：2008-06-10
申请号：US10830390
申请日：2004-04-21
申请人： Hyung-Shin Kwon , Joon-Yong Joo , Kwang-Ok Koh , Sung-Bong Kim
发明人： Hyung-Shin Kwon , Joon-Yong Joo , Kwang-Ok Koh , Sung-Bong Kim
IPC分类号： H01L29/861
CPC分类号： H01L29/66507 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/6653 , H01L29/66545
摘要： The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 Å in the impurity region.
摘要翻译：本发明提供一种具有硅化物薄膜的半导体器件及其形成方法。半导体器件包括形成在半导体衬底的有源区上的栅极绝缘层。在栅极绝缘层上形成栅电极。在与栅电极相邻的有源区中形成杂质区。诸如硅化钴薄膜的硅化物薄膜在杂质区域中形成为小于约200埃的厚度。

46. 发明申请

US20050142209A1 Aqueous alkaline solution for mineral supplementation, preparing method thereof and composition for prevention and improvement of osteoporosis containing the same 审中-公开
标题翻译：矿物质补充用碱性水溶液，其制备方法以及预防和改善含有其的骨质疏松症的组合物
公开(公告)号：US20050142209A1
公开(公告)日：2005-06-30
申请号：US10823915
申请日：2004-04-14
申请人： Seong-Yung Hwa , Young-Chul Jung , Sung-Sik Chun , Shin-Kwon Kang , Jong-Kwon Seo
发明人： Seong-Yung Hwa , Young-Chul Jung , Sung-Sik Chun , Shin-Kwon Kang , Jong-Kwon Seo
IPC分类号： A61K35/56 , A23L1/30 , A23L1/304 , A61K31/19 , A61K31/202 , A61K35/32 , A61K36/00 , A61K36/02 , A61K38/17 , A61K35/78 , A61K35/80
CPC分类号： A61K31/202 , A23L33/105 , A23L33/16 , A23V2002/00 , A61K31/19 , A61K35/32 , A61K36/04 , A61K36/07 , A61K36/076 , A61K36/232 , A61K36/234 , A61K36/46 , A61K36/48 , A61K36/481 , A61K36/484 , A61K36/65 , A61K36/734 , A61K36/804 , A61K36/882 , A61K36/8945 , A61K2300/00 , A23V2200/306 , A23V2250/204 , A23V2250/202 , A23V2250/02 , A23V2250/21 , A23V2250/1868
摘要： The present invention relates to an aqueous alkaline solution for mineral supplementation comprising bovine bones, cuttlefish bones, red algae and an organic acid. Also, the invention relates to a method for preparing the aqueous alkaline solution, and a composition or health food containing the aqueous alkaline solution, which is effective in the prevention and improvement in osteoporosis. The aqueous alkaline solution contains various minerals necessary for the human body at large amounts, and thus, can be used as a mineral supplement. Also, the composition prevents bone absorption and bone mineral absorption, and thus, is useful for the prevention and improvement of bone diseases, such as osteoporosis and degenerative bone diseases.
摘要翻译：本发明涉及一种矿物质补充剂的碱性水溶液，其包括牛骨，乌贼骨，红藻和有机酸。此外，本发明涉及一种制备碱性水溶液的方法，以及含有碱性水溶液的组合物或保健食品，其有效预防和改善骨质疏松症。碱性水溶液含有大量人体所需的各种矿物质，因此可以作为矿物质补充剂使用。此外，该组合物可防止骨吸收和骨矿物质吸收，因此可用于预防和改善骨疾病如骨质疏松症和退行性骨病。

47. 发明授权

US06635539B2 Method for fabricating a MOS transistor using a self-aligned silicide technique 失效
公开(公告)号：US06635539B2
公开(公告)日：2003-10-21
申请号：US10131418
申请日：2002-04-22
申请人： Hyung-Shin Kwon , Do-Hyung Kim
发明人： Hyung-Shin Kwon , Do-Hyung Kim
IPC分类号： H01L21336
CPC分类号： H01L29/66507 , H01L29/66545
摘要： A method for fabricating a MOS transistor using a self-aligned silicide technique is provided. The method includes forming a gate electrode and a silicidation resistant layer pattern that are sequentially stacked on a predetermined region of a semiconductor substrate. Impurities are implanted into the semiconductor substrate to form a source/drain region. A first metal silicide layer is selectively formed on the surface of the source/drain region. The silicidation resistant layer pattern is then removed to expose the gate electrode. A second metal silicide layer is selectively formed on the exposed gate electrode. Consequently, the first metal silicide layer can be formed of a metal silicide layer having superior tolerance with respect to junction spiking. Also, the second metal silicide layer can be formed of another metal silicide layer having a low variation of resistivity due to the variation of the line width of the gate electrode. Therefore, it is possible to fabricate a high-performance MOS transistor suitable for a highly integrated semiconductor device.

48. 发明授权

US06617700B2 Repairable multi-chip package and high-density memory card having the package 失效
公开(公告)号：US06617700B2
公开(公告)日：2003-09-09
申请号：US09923669
申请日：2001-08-06
申请人： Joon-Ki Lee , Young-Hee Song , Young-Shin Kwon
发明人： Joon-Ki Lee , Young-Hee Song , Young-Shin Kwon
IPC分类号： H01L2328
CPC分类号： H01L23/5382 , H01L24/45 , H01L24/48 , H01L25/0655 , H01L2224/05553 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/10161 , H01L2924/12042 , H01L2924/14 , H01L2924/15192 , H01L2924/181 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： Disclosed are a repairable multi-chip package and a high-density memory card having the multi-chip package. The package includes a circuit substrate having bonding tips on a first surface and external contact pads on a second surface opposite to the first surface. The bonding tips and the external contact pads are electrically connected to each other. The package also includes at least two memory chips each mounted on the first surface and having chip pads thereon. The package includes electrically connecting members coupling each bonding tip to each chip pad, and an encapsulation layer covering the chips and the electrically connecting members. Particularly, the encapsulation layer is divided into two or more parts, and the bonding tips are partially embedded in and partially exposed out of the divided encapsulation layer. Accordingly, the exposed bonding tips can be selectively cut or re-connected for repairing the multi-chip package. Additionally, a high-density memory card having the package is also disclosed.

49. 发明申请

US20150311433A1 SEMICONDUCTOR DEVICE, MAGNETIC MEMORY DEVICE, AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件，磁存储器件及其制造方法
公开(公告)号：US20150311433A1
公开(公告)日：2015-10-29
申请号：US14606157
申请日：2015-01-27
申请人： Byoungjae BAE , Jongchul PARK , Shin KWON , Inho KIM , Changwoo SUN
发明人： Byoungjae BAE , Jongchul PARK , Shin KWON , Inho KIM , Changwoo SUN
IPC分类号： H01L43/12 , H01L27/22 , H01L43/08
CPC分类号： H01L43/12 , H01L27/228 , H01L43/08
摘要： A method of fabricating a semiconductor device includes forming conductive pillars on a substrate, sequentially forming a sacrificial layer and a molding structure between the conductive pillars, forming a conductive layer on the molding structure, such that the conductive layer is connected to the conductive pillars, removing the sacrificial layer to form an air gap, removing the molding structure to form an expanded air gap, and patterning the conductive layer to open the expanded air gap.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成导电柱，在导电柱之间依次形成牺牲层和模制结构，在模制结构上形成导电层，使得导电层连接到导电柱上，去除牺牲层以形成气隙，去除模制结构以形成扩张空气间隙，并且图案化导电层以打开膨胀的气隙。

50. 发明授权

US09113545B2 Tape wiring substrate and chip-on-film package including the same 有权
标题翻译：带状布线基板和包括其的片上胶片封装
公开(公告)号：US09113545B2
公开(公告)日：2015-08-18
申请号：US13604412
申请日：2012-09-05
申请人： Sang-uk Han , Young-shin Kwon , Kwan-jai Lee , Jae-min Jung , Kyong-soon Cho , Jeong-kyu Ha
发明人： Sang-uk Han , Young-shin Kwon , Kwan-jai Lee , Jae-min Jung , Kyong-soon Cho , Jeong-kyu Ha
IPC分类号： H05K1/00 , H05K7/00 , H05K1/02 , H05K3/32 , H05K1/14 , H05K1/18
CPC分类号： H05K7/00 , H05K1/028 , H05K1/147 , H05K1/189 , H05K3/323 , H05K2201/09036 , H05K2201/10128
摘要： A tape wiring substrate includes a base film having at least one recess in a first surface of the base film and a chip-mounting region on which a semiconductor chip is included on a second surface of the base film. A wiring pattern is formed on the second surface of the base film and is extended to an edge of the chip-mounting region. A protection film covers the wiring pattern.
摘要翻译：带状布线基板包括在基膜的第一表面中具有至少一个凹部的基膜和在基膜的第二表面上包含半导体芯片的芯片安装区域。在基膜的第二表面上形成布线图案并延伸到芯片安装区域的边缘。保护膜覆盖布线图案。

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