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1. 发明授权

US09113545B2 Tape wiring substrate and chip-on-film package including the same 有权
标题翻译：带状布线基板和包括其的片上胶片封装
公开(公告)号：US09113545B2
公开(公告)日：2015-08-18
申请号：US13604412
申请日：2012-09-05
申请人： Sang-uk Han , Young-shin Kwon , Kwan-jai Lee , Jae-min Jung , Kyong-soon Cho , Jeong-kyu Ha
发明人： Sang-uk Han , Young-shin Kwon , Kwan-jai Lee , Jae-min Jung , Kyong-soon Cho , Jeong-kyu Ha
IPC分类号： H05K1/00 , H05K7/00 , H05K1/02 , H05K3/32 , H05K1/14 , H05K1/18
CPC分类号： H05K7/00 , H05K1/028 , H05K1/147 , H05K1/189 , H05K3/323 , H05K2201/09036 , H05K2201/10128
摘要： A tape wiring substrate includes a base film having at least one recess in a first surface of the base film and a chip-mounting region on which a semiconductor chip is included on a second surface of the base film. A wiring pattern is formed on the second surface of the base film and is extended to an edge of the chip-mounting region. A protection film covers the wiring pattern.
摘要翻译：带状布线基板包括在基膜的第一表面中具有至少一个凹部的基膜和在基膜的第二表面上包含半导体芯片的芯片安装区域。在基膜的第二表面上形成布线图案并延伸到芯片安装区域的边缘。保护膜覆盖布线图案。

2. 发明授权

US08575735B2 Semiconductor chip and film and TAB package comprising the chip and film 有权
标题翻译：半导体芯片和薄膜以及包括芯片和薄膜的TAB封装
公开(公告)号：US08575735B2
公开(公告)日：2013-11-05
申请号：US13034973
申请日：2011-02-25
申请人： Young-Sang Cho , Chang-Sig Kang , Dae-Woo Son , Yun-Seok Choi , Kyong-Soon Cho , Sang-Heul Lee
发明人： Young-Sang Cho , Chang-Sig Kang , Dae-Woo Son , Yun-Seok Choi , Kyong-Soon Cho , Sang-Heul Lee
IPC分类号： H01L23/495
CPC分类号： H01L24/50 , H01L23/4985 , H01L24/06 , H01L2224/0401 , H01L2224/0405 , H01L2224/05553 , H01L2224/06155 , H01L2224/14155 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14
摘要： A semiconductor chip for a tape automated bonding (TAB) package is disclosed. The semiconductor chip comprises a connection surface including a set of input pads connected to internal circuitry of the chip and for conveying external signals to the internal circuitry, the set of input pads comprising all of the input pads on the chip. The connection surface includes a set of output pads connected to internal circuitry of the chip and for conveying internal chip signals to outside the chip, the set of output pads comprising all of the output pads on the chip.
摘要翻译：公开了一种用于带式自动接合（TAB）封装的半导体芯片。半导体芯片包括连接表面，其包括连接到芯片的内部电路的一组输入焊盘，并且用于将外部信号传送到内部电路，该组输入焊盘包括芯片上的所有输入焊盘。连接表面包括连接到芯片的内部电路的一组输出焊盘，并将内部芯片信号传送到芯片外部，该组输出焊盘包括芯片上的所有输出焊盘。

3. 发明申请

US20090273076A1 Tape for heat dissipating member, chip on film type semiconductor package including heat dissipating member, and elctronic apparatus including the same 有权
标题翻译：用于散热构件的胶带，包括散热构件的薄膜型半导体封装的芯片，以及包括该散热构件的电子装置
公开(公告)号：US20090273076A1
公开(公告)日：2009-11-05
申请号：US12385731
申请日：2009-04-17
申请人： Kyong-sei CHOI , Byung-seo Kim , Young-jae Joo , Ye-chung Chung , Kyong-soon Cho , Sang-heui Lee , Si-hoon Lee , Sa-yoon Kang , Dae-woo Son , Sang-gui Jo , Jeong-kyu Ha , Young-sang Cho
发明人： Kyong-sei CHOI , Byung-seo Kim , Young-jae Joo , Ye-chung Chung , Kyong-soon Cho , Sang-heui Lee , Si-hoon Lee , Sa-yoon Kang , Dae-woo Son , Sang-gui Jo , Jeong-kyu Ha , Young-sang Cho
IPC分类号： H01L23/498 , H01L23/36
CPC分类号： H01L23/49838 , H01L23/4985 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01079 , H05K1/0203 , H05K1/189 , H05K2201/09109 , H05K2201/1028 , H05K2201/10674 , H05K2203/1581 , H01L2924/00
摘要： Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.
摘要翻译：公开了一种片上胶片（COF）型半导体封装以及使用其的器件。 COF型半导体封装可以包括包括顶表面和底表面的绝缘衬底，绝缘衬底的顶表面上的半导体器件，绝缘衬底的底表面上的散热部件，以及绝缘衬底的至少一个空间绝缘基板的底表面和散热部件的顶表面。

4. 发明申请

US20120274868A1 Semiconductor Package 有权
标题翻译：半导体封装
公开(公告)号：US20120274868A1
公开(公告)日：2012-11-01
申请号：US13427435
申请日：2012-03-22
申请人： Kyong-soon Cho , Seung-kon Mok , Kwan-jai Lee , Jae-min Jung
发明人： Kyong-soon Cho , Seung-kon Mok , Kwan-jai Lee , Jae-min Jung
IPC分类号： G02F1/133 , H01L23/02
CPC分类号： G02F1/133 , H01L23/3121 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/01322 , H01L2924/3025 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor package may include a substrate, a semiconductor chip disposed on the substrate, a communication terminal and a static electricity inducing terminal connected to a ground. The package may include a first sealant that comprises a voltage sensitive material and that covers the semiconductor chip and a static electricity blocking layer that provides a conductive pathway from the first sealant to only the static electric inducing terminal. The static electricity blocking layer may prevent the communication terminal from being electrically connected to the first sealant. If a buildup of charge is applied to the device, the first sealant may become polarized and/or conductive. The extra voltage may travel through the first sealant to the static electricity inducing terminal via an opening in the static electricity blocking layer. The semiconductor chip and the communication terminal may not be affected by the extra charge.
摘要翻译：半导体封装可以包括衬底，设置在衬底上的半导体芯片，连接到地的通信终端和静电诱导终端。封装可以包括第一密封剂，其包括电压敏感材料并且覆盖半导体芯片和静电阻挡层，静电阻挡层提供从第一密封剂到仅静电导电端子的导电路径。静电阻止层可以防止通信端子与第一密封剂电连接。如果对器件施加电荷累积，则第一密封剂可能变得极化和/或导电。额外的电压可以通过静电阻挡层中的开口穿过第一密封剂到静电诱导端子。半导体芯片和通信终端可能不受额外的电荷的影响。

5. 发明申请

US20110210433A1 SEMICONDUCTOR CHIP AND FILM AND TAB PACKAGE COMPRISING THE CHIP AND FILM 有权
标题翻译：半导体芯片和薄膜和包装芯片和薄膜的包装
公开(公告)号：US20110210433A1
公开(公告)日：2011-09-01
申请号：US13034973
申请日：2011-02-25
申请人： Young-Sang Cho , Chang-Sig Kang , Dae-Woo Son , Yun-Seok Choi , Kyong-Soon Cho , Sang-Heul Lee
发明人： Young-Sang Cho , Chang-Sig Kang , Dae-Woo Son , Yun-Seok Choi , Kyong-Soon Cho , Sang-Heul Lee
IPC分类号： H01L23/495 , H01L23/48
CPC分类号： H01L24/50 , H01L23/4985 , H01L24/06 , H01L2224/0401 , H01L2224/0405 , H01L2224/05553 , H01L2224/06155 , H01L2224/14155 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14
摘要： A semiconductor chip for a tape automated bonding (TAB) package is disclosed. The semiconductor chip comprises a connection surface including a set of input pads connected to internal circuitry of the chip and for conveying external signals to the internal circuitry, the set of input pads comprising all of the input pads on the chip. The connection surface includes a set of output pads connected to internal circuitry of the chip and for conveying internal chip signals to outside the chip, the set of output pads comprising all of the output pads on the chip. The connection surface includes a first edge and a second edge that are substantially parallel to each other and are opposite each other on a respective first side and second side of the chip, and a third edge and fourth edge that are substantially perpendicular to the first and second edges, and are opposite each other on a respective third side and fourth side of the chip. A plurality of input pads of the set of input pads are adjacent the first edge, and are arranged in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads of the set of output pads are adjacent the second edge, and are arranged in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads of the set of output pads are located between the first row and the second row. The plurality of second output pads include at least first and second outermost pads located a certain distance from the respective third edge and fourth edge, and at least first and second inner pads located a greater distance from the respective third edge and fourth edge than the first and second outermost pads.
摘要翻译：公开了一种用于带式自动接合（TAB）封装的半导体芯片。半导体芯片包括连接表面，其包括连接到芯片的内部电路的一组输入焊盘，并且用于将外部信号传送到内部电路，该组输入焊盘包括芯片上的所有输入焊盘。连接表面包括连接到芯片的内部电路的一组输出焊盘，并将内部芯片信号传送到芯片外部，该组输出焊盘包括芯片上的所有输出焊盘。所述连接表面包括第一边缘和第二边缘，所述第一边缘和第二边缘基本上彼此平行并且在所述芯片的相应的第一侧面和第二侧上彼此相对;以及第三边缘和第四边缘，所述第三边缘和第四边缘基本上垂直于所述第一和第二边缘，第二边缘，并且在芯片的相应的第三侧面和第四侧上彼此相对。所述一组输入焊盘的多个输入焊盘与第一边缘相邻，并且布置在基本上平行于第一边缘并沿第一方向延伸的第一行中; 所述一组输出焊盘的多个第一输出焊盘与所述第二边缘相邻，并且布置在基本上平行于所述第二边缘并沿所述第一方向延伸的第二行中; 并且该组输出焊盘的多个第二输出焊盘位于第一行和第二行之间。多个第二输出焊盘包括至少第一和第二最外面的焊盘，其位于距相应的第三边缘和第四边缘一定距离处，并且至少第一和第二内部焊盘位于相对于第三边缘和第四边缘的距离比第一边缘和第二最外面的垫。

6. 发明申请

US20100005652A1 Method of manufacturing a wiring substrate, method of manufacturing a tape package and method of manufacturing a display device 审中-公开
标题翻译：布线基板的制造方法，带状封装的制造方法以及显示装置的制造方法
公开(公告)号：US20100005652A1
公开(公告)日：2010-01-14
申请号：US12458430
申请日：2009-07-13
申请人： Dong-Han Kim , Kyoung-Sei Choi , Kyong-Soon Cho
发明人： Dong-Han Kim , Kyoung-Sei Choi , Kyong-Soon Cho
IPC分类号： H05K3/20 , H01S4/00
CPC分类号： H05K3/207 , H05K1/0393 , H05K3/1216 , H05K3/386 , H05K2203/0113 , Y10T29/49002 , Y10T29/49128 , Y10T29/4913
摘要： Disclosed is a method of manufacturing a wiring substrate, a tape package using the wiring substrate, and a display device using the wiring substrate. In a method of manufacturing a wiring substrate, a screen may be disposed on a base plate, the screen having openings for forming wirings. A conductive paste may be coated in the openings of the screen. A substrate may be on the screen, the conductive paste being coated in the openings of the screen. The conductive paste may be hardened to be adhered to the substrate. The base plate and the screen may be removed from the substrate to form wirings on the substrate. Because the wirings may be formed using a glass substrate having heat-resisting properties by simplified processes, thermal deflections of the substrate and dimension variations in manufacturing processes may be reduced or minimized.
摘要翻译：公开了一种制造布线基板的方法，使用该布线基板的带封装以及使用该布线基板的显示装置。在制造布线基板的方法中，可以在基板上设置屏幕，该屏幕具有用于形成布线的开口。可以在屏幕的开口中涂覆导电糊。衬底可以在屏幕上，导电膏被涂覆在屏幕的开口中。导电膏可以硬化以粘附到基底上。基板和屏幕可以从基板移除以在基板上形成布线。由于可以通过简化的工艺使用具有耐热性的玻璃基板形成布线，所以可以减小或最小化基板的热偏转和制造工艺中的尺寸变化。

7. 发明申请

US20120074540A1 SEMICONDUCTOR CHIP PACKAGE 有权
标题翻译：半导体芯片包装
公开(公告)号：US20120074540A1
公开(公告)日：2012-03-29
申请号：US13181920
申请日：2011-07-13
申请人： Kyong-Soon CHO , Chang-Su KIM , Kwan-Jai LEE , Kyoung-Sei CHOI , Jae-Hyok KO , Keung-Beum Kim
发明人： Kyong-Soon CHO , Chang-Su KIM , Kwan-Jai LEE , Kyoung-Sei CHOI , Jae-Hyok KO , Keung-Beum Kim
IPC分类号： H01L23/552
CPC分类号： H01L23/60 , H01L23/13 , H01L23/3121 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/48235 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a plurality of electrode pads on a second surface, different from the first surface, of the substrate; and an electrostatic discharge protection pad overlapping a portion of a first electrode pad and a portion of a second electrode pad among the plurality of electrode pads.
摘要翻译：提供半导体芯片封装的结构。半导体芯片封装包括：基板; 安装在所述基板的第一表面上的半导体芯片; 与基板的第一表面不同的第二表面上的多个电极焊盘; 以及与所述多个电极焊盘中的第一电极焊盘的一部分和第二电极焊盘的一部分重叠的静电放电保护焊盘。

8. 发明授权

US08803301B2 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US08803301B2
公开(公告)日：2014-08-12
申请号：US13427435
申请日：2012-03-22
申请人： Kyong-soon Cho , Seung-kon Mok , Kwan-jai Lee , Jae-min Jung
发明人： Kyong-soon Cho , Seung-kon Mok , Kwan-jai Lee , Jae-min Jung
IPC分类号： H01L23/495
CPC分类号： G02F1/133 , H01L23/3121 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/01322 , H01L2924/3025 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor package may include a substrate, a semiconductor chip disposed on the substrate, a communication terminal and a static electricity inducing terminal connected to a ground. The package may include a first sealant that comprises a voltage sensitive material and that covers the semiconductor chip and a static electricity blocking layer that provides a conductive pathway from the first sealant to only the static electric inducing terminal. The static electricity blocking layer may prevent the communication terminal from being electrically connected to the first sealant. If a buildup of charge is applied to the device, the first sealant may become polarized and/or conductive. The extra voltage may travel through the first sealant to the static electricity inducing terminal via an opening in the static electricity blocking layer. The semiconductor chip and the communication terminal may not be affected by the extra charge.
摘要翻译：半导体封装可以包括衬底，设置在衬底上的半导体芯片，连接到地的通信终端和静电诱导终端。封装可以包括第一密封剂，其包括电压敏感材料并且覆盖半导体芯片和静电阻挡层，静电阻挡层提供从第一密封剂到仅静电导电端子的导电路径。静电阻止层可以防止通信端子与第一密封剂电连接。如果对器件施加电荷累积，则第一密封剂可能变得极化和/或导电。额外的电压可以通过静电阻挡层中的开口穿过第一密封剂到静电诱导端子。半导体芯片和通信终端可能不受额外的电荷的影响。

9. 发明申请

US20130148312A1 TAPE WIRING SUBSTRATE AND CHIP-ON-FILM PACKAGE INCLUDING THE SAME 有权
标题翻译：带子接线基片和片上电影包装盒，包括它们
公开(公告)号：US20130148312A1
公开(公告)日：2013-06-13
申请号：US13604412
申请日：2012-09-05
申请人： Sang-Uk Han , Young-Shin Kwon , Kwan-Jai Lee , Jae-Min Jung , Kyong-Soon Cho , Jeong-Kyu Ha
发明人： Sang-Uk Han , Young-Shin Kwon , Kwan-Jai Lee , Jae-Min Jung , Kyong-Soon Cho , Jeong-Kyu Ha
IPC分类号： H05K7/00
CPC分类号： H05K7/00 , H05K1/028 , H05K1/147 , H05K1/189 , H05K3/323 , H05K2201/09036 , H05K2201/10128
摘要： A tape wiring substrate includes a base film having at least one recess in a first surface of the base film and a chip-mounting region on which a semiconductor chip is included on a second surface of the base film. A wiring pattern is formed on the second surface of the base film and is extended to an edge of the chip-mounting region. A protection film covers the wiring pattern.
摘要翻译：带状布线基板包括在基膜的第一表面中具有至少一个凹部的基膜和在基膜的第二表面上包含半导体芯片的芯片安装区域。在基膜的第二表面上形成布线图案并延伸到芯片安装区域的边缘。保护膜覆盖布线图案。

10. 发明申请

US20110143625A1 TAPE FOR HEAT DISSIPATING MEMBER, CHIP ON FILM TYPE SEMICONDUCTOR PACKAGE INCLUDING HEAT DISSIPATING MEMBER, AND ELECTRONIC APPARATUS INCLUDING THE SAME 有权
标题翻译：用于散热构件的胶带，薄膜型半导体封装，包括散热构件的芯片，以及包括其的电子设备
公开(公告)号：US20110143625A1
公开(公告)日：2011-06-16
申请号：US13033307
申请日：2011-02-23
申请人： Kyoung-sei Choi , Byung-seo Kim , Young-jae Joo , Ye-chung Chung , Kyong-soon Cho , Sang-heui Lee , Si-hoon Lee , Sa-yoon Kang , Dae-woo Son , Sang-gui Jo , Jeong-kyu Ha , Young-sang Cho
发明人： Kyoung-sei Choi , Byung-seo Kim , Young-jae Joo , Ye-chung Chung , Kyong-soon Cho , Sang-heui Lee , Si-hoon Lee , Sa-yoon Kang , Dae-woo Son , Sang-gui Jo , Jeong-kyu Ha , Young-sang Cho
IPC分类号： H01J9/00
CPC分类号： H01L23/49838 , H01L23/4985 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01079 , H05K1/0203 , H05K1/189 , H05K2201/09109 , H05K2201/1028 , H05K2201/10674 , H05K2203/1581 , H01L2924/00
摘要： Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.
摘要翻译：公开了一种片上胶片（COF）型半导体封装以及使用其的器件。 COF型半导体封装可以包括包括顶表面和底表面的绝缘衬底，绝缘衬底的顶表面上的半导体器件，绝缘衬底的底表面上的散热部件，以及绝缘衬底的至少一个空间绝缘基板的底表面和散热部件的顶表面。

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