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41. 发明授权

US08418113B1 Consideration of local routing and pin access during VLSI global routing 失效
标题翻译：在VLSI全局路由期间考虑本地路由和引脚接入
公开(公告)号：US08418113B1
公开(公告)日：2013-04-09
申请号：US13252067
申请日：2011-10-03
申请人： Charles J. Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
发明人： Charles J. Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the wiring track capacity for an edge is reduced based on the pin information. After global routing, the wiring track capacities are increased by previous reduction amounts for detailed routing. The pin information can include pin count for an associated tile, the Steiner tree length for the pins, or relative locations of the pins. Wiring track capacities are preferably reduced by creating blockages in tracks of a particular metal layer of the circuit design used for logic gates of the pins. The blockage tracks can be spread evenly across the wiring tracks of a given edge.
摘要翻译：通过考虑本地路由和引脚访问来增强全局路由和拥塞评估。针对每个全局边缘基于相邻瓦片计算引脚信息，并且基于引脚信息减少边缘的布线轨迹容量。在全局路由之后，为了详细路由，线路轨道容量会增加先前的减少量。引脚信息可以包括相关瓦片的引脚数，引脚的Steiner树长度或引脚的相对位置。优选地通过在用于针的逻辑门的电路设计的特定金属层的轨道中产生阻塞来减少接线轨迹容量。阻塞轨道可以均匀地分布在给定边缘的接线轨道上。

42. 发明授权

US08418108B2 Accuracy pin-slew mode for gate delay calculation 失效
标题翻译：用于门延迟计算的精度针脚转换模式
公开(公告)号：US08418108B2
公开(公告)日：2013-04-09
申请号：US13162806
申请日：2011-06-17
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan , Brian C. Wilson
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan , Brian C. Wilson
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031 , G06F2217/84
摘要： The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.
摘要翻译：通过将默认转换速率分配给先前逻辑级的输出门，该值大于设计的中间转换速率来计算集成电路设计选定门的输入。该默认转换速率通过逻辑级传播，以在所选择的门产生输入转换速率。默认转换速率对应于应用于设计中随机选择的门的初步压摆率的有限样本的预定百分位数。作为第二逻辑级中从输出门到第一门的线长度的已知特性的函数调整默认转换速率。基于输入转换速率来计算所选择的门的延迟。输入转换速率可以在一次优化迭代期间存储，并在以后的优化迭代中用作默认转换速率。

43. 发明申请

US20130086537A1 Design Routability Using Multiplexer Structures 失效
标题翻译：使用多路复用器结构设计路由
公开(公告)号：US20130086537A1
公开(公告)日：2013-04-04
申请号：US13248119
申请日：2011-09-29
申请人： Charles J. Alpert , Victor N. Kravets , Zhuo Li , Louise H. Trevillyan , Ying Zhou
发明人： Charles J. Alpert , Victor N. Kravets , Zhuo Li , Louise H. Trevillyan , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Mechanisms are provided for generating a logic design of an integrated circuit device. An initial logic design representation of the integrated circuit device is received and one or more areas of the initial logic design representation are identified where logic elements in the one or more areas can be replaced with one or more multiplexer tree structures. Logic elements in the one or more areas of the initial logic design representation are replaced with multiplexer tree structures to generate a modified logic design representation. The modified logic design representation is output to a physical synthesis system to generate a physical layout of the integrated circuit device based on the modified logic design representation.
摘要翻译：提供用于产生集成电路器件的逻辑设计的机构。接收集成电路设备的初始逻辑设计表示，并且识别初始逻辑设计表示的一个或多个区域，其中一个或多个区域中的逻辑元件可被一个或多个多路复用器树结构替代。初始逻辑设计表示的一个或多个区域中的逻辑元件被多路复用器树结构替代以生成修改的逻辑设计表示。经修改的逻辑设计表示被输出到物理合成系统，以基于经修改的逻辑设计表示来生成集成电路器件的物理布局。

44. 发明申请

US20120266124A1 Placement of Structured Nets 有权
标题翻译：结构网的布置
公开(公告)号：US20120266124A1
公开(公告)日：2012-10-18
申请号：US13086428
申请日：2011-04-14
申请人： Charles J. Alpert , Myung-Chul Kim , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
发明人： Charles J. Alpert , Myung-Chul Kim , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Mechanisms are provided for performing placement of cells in a design of a semiconductor device. An initial design of the semiconductor device is generated, the initial design comprising a first placement of cells. A preferred direction of placement associated with the cells is determined. The preferred direction is a direction along which spreading of the cells is preferred. A second design of the semiconductor device is generated by modifying the first placement of the cells to generate a second placement of cells, different from the first placement cells, based on the preferred direction of placement associated with the cells.
摘要翻译：提供了用于在半导体器件的设计中执行电池放置的机构。生成半导体器件的初始设计，初始设计包括单元的第一放置。确定与细胞相关联的放置的优选方向。优选的方向是细胞扩散优选的方向。基于与单元相关联的放置的优选方向，通过修改单元的第一放置以产生与第一放置单元不同的单元的第二放置来生成半导体器件的第二设计。

45. 发明申请

US20120144358A1 Resolving Global Coupling Timing and Slew Violations for Buffer-Dominated Designs 有权
标题翻译：解决缓冲区主导设计的全局耦合时序和摆动违例
公开(公告)号：US20120144358A1
公开(公告)日：2012-06-07
申请号：US12959029
申请日：2010-12-02
申请人： Charles J. Alpert , Clabes G. Joachim , Zhuo Li , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Clabes G. Joachim , Zhuo Li , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/84
摘要： A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is rentable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated.
摘要翻译：提供了一种机制，用于在集成电路（IC）设计中解决提升或耦合时序问题和转换冲突，而不会牺牲延迟模式时序。响应于针对新IC设计中的多个网络中的每个网络而接收的用于生成新的IC设计的请求，确定网络是否可以通过使用成本函数的多个小区中的小区可租借与电池相关联，使得与网络相关联的耦合电容等于或低于预定的耦合电容阈值。响应于网络能够通过耦合电容等于或低于门限路由到小区，网络被分配给小区内的至少一个轨道。对于正在路由的新IC设计中的所有网络，生成新的IC设计。

46. 发明申请

US20110302545A1 DETAILED ROUTABILITY BY CELL PLACEMENT 有权
标题翻译：细节放置的详细的不可靠性
公开(公告)号：US20110302545A1
公开(公告)日：2011-12-08
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

47. 发明授权

US08010926B2 Clock power minimization with regular physical placement of clock repeater components 失效
标题翻译：时钟功率最小化，具有定时物理放置的时钟中继器组件
公开(公告)号：US08010926B2
公开(公告)日：2011-08-30
申请号：US12022849
申请日：2008-01-30
申请人： Charles J. Alpert , Ruchir Puri , Shyam Ramji , Ashish K. Singh , Chin Ngai Sze
发明人： Charles J. Alpert , Ruchir Puri , Shyam Ramji , Ashish K. Singh , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/62
摘要： Power, routability and electromigration have become crucial issues in modern microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance on the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally place clock components in a regular fashion so as to minimize clock power within a performance constraint. A rectangular grid is created and clock distribution structures are assigned to the grid intersection points. Latches are then located around the clock distribution structures to minimize an overall distance for connections between the latches and respective clock distribution structures. The horizontal and vertical pitches of the grid may be independently adjusted to achieve a more uniform spread of the clock distribution structures.
摘要翻译：电力，可布线性和电迁移在现代微处理器设计中成为关键问题。在高性能设计中，时钟是功耗最大的消费者。排列时钟元件的规律性，以便最小化时钟网络上的电容可以帮助降低时钟功率，但是，由于物理放置这些组件的灵活性会有所损失，可能会损害性能。本发明提供了以规则方式最佳地放置时钟组件以便在性能约束内最小化时钟功率的技术。创建矩形网格，并将时钟分配结构分配给网格交点。然后锁存器位于时钟分布结构周围，以最小化锁存器和相应时钟分配结构之间的连接的总距离。可以独立地调整网格的水平和垂直间距以实现时钟分配结构的更均匀的扩展。

48. 发明授权

US07934188B2 Legalization of VLSI circuit placement with blockages using hierarchical row slicing 有权
标题翻译： VLSI电路放置合法化使用分层行分片
公开(公告)号：US07934188B2
公开(公告)日：2011-04-26
申请号：US12108599
申请日：2008-04-24
申请人： Charles J. Alpert , Michael W. Dotson , Gi-Joon Nam , Shyam Ramji , Natarajan Viswanathan
发明人： Charles J. Alpert , Michael W. Dotson , Gi-Joon Nam , Shyam Ramji , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and the large blockages without regard to small blockages (while satisfying capacity constraints of the coarse regions), and thereafter the movable logic cells are relocated among fine regions between small blockages to remove all cell overlaps (while satisfying capacity constraints of the fine regions). The coarse and fine regions may be horizontal slices of the placement region having a height corresponding to a single circuit row height of the design. Cells are relocated with minimal perturbation from the previous placement, preserving wirelength and timing optimizations. The legalization technique may utilize more than two levels of granularity with multiple relocation stages.
摘要翻译：在存在阻塞的情况下使逻辑单元的放置合法化的分级方法根据大小（大和小）选择性地将阻塞分类为至少两个不同的集合。可移动逻辑单元首先在大阻塞之间的粗略区域中重新定位，以消除单元和大阻塞之间的重叠，而不考虑小的阻塞（同时满足粗略区域的容量约束），然后将可移动逻辑单元重新定位在小的堵塞以消除所有的细胞重叠（同时满足精细区域的容量限制）。粗细区域可以是具有对应于设计的单个电路行高度的高度的放置区域的水平切片。细胞被重新定位，从最初的位置移动，保持线长和时序优化。合法化技术可以利用具有多个重定位阶段的多于两个级别的粒度。

49. 发明授权

US07895557B2 Concurrent buffering and layer assignment in integrated circuit layout 有权
标题翻译：集成电路布局中的并行缓冲和层分配
公开(公告)号：US07895557B2
公开(公告)日：2011-02-22
申请号：US12100477
申请日：2008-04-10
申请人： Charles J. Alpert , Zhuo Li , Tuhin Mahmud , Stephen T. Quay , Paul G. Villarrubla
发明人： Charles J. Alpert , Zhuo Li , Tuhin Mahmud , Stephen T. Quay , Paul G. Villarrubla
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5045 , G06F17/505
摘要： A method and system for concurrent buffering and layer assignment in integrated current layout. Buffers are inserted and metal interconnects or “wires” are sized for every net, which consists of one driver and one or more receivers, such that timing skew constraints can be met. Long nets are promoted to a higher level if the slew violation can be fixed only by a promotion of the net or if the “slack” gain available by this promotion is equal to or greater than a predesignated layer of promotion threshold. In response to determining these layer assignments, the method and system then systematically demotes nets that are not critical and which do not impact the circuit and electrical constraints in order to minimize the use of high layer wire resources.
摘要翻译：一种集成电流布局中并发缓存和层分配的方法和系统。插入缓冲器，并且每个网络的金属互连或“电线”的大小适合于由一个驱动器和一个或多个接收器组成的网络，从而可以满足定时偏移约束。如果可以通过网络的推广来修复浪费的违规行为，或者如果该促销活动可用的“松弛”收益等于或大于预先指定的促销门槛层，长网将被提升到更高的水平。响应于确定这些层分配，该方法和系统然后系统地降低不关键且不影响电路和电气约束的网，以便最小化高层线材资源的使用。

50. 发明授权

US07890905B2 Slew constrained minimum cost buffering 有权
标题翻译：压缩约束最低成本缓冲
公开(公告)号：US07890905B2
公开(公告)日：2011-02-15
申请号：US12168153
申请日：2008-07-06
申请人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.
摘要翻译：缓冲插入技术解决了压摆约束，同时最大限度地减少了缓冲区成本。该方法构建了汇的初始解决方案，每个都具有相关的成本，压摆和电容。当解决方案向源传播时，将线电容和线压力加到解决方案中。当选择缓冲器进行可能的插入时，将解决方案的电压设置为零，同时根据所选择的缓冲器增加解决方案的成本，并将电容设置为缓冲器的固有电容。通过增加分支电容和成本，并选择最高的分支电压，合并两条相交线分支的解决方案。解决方案集通过忽略具有大于压摆约束的转矩分量的解决方案来更新，并且消除由另一解决方案主导的任何解决方案。选择具有最小成本的解决方案作为最终解决方案。

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