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31. 发明授权

US06683476B2 Contact ring architecture 失效
标题翻译：联系环架构
公开(公告)号：US06683476B2
公开(公告)日：2004-01-27
申请号：US10140967
申请日：2002-05-08
申请人： Anwar Ali , Tauman T. Lau , Max M. Yeung
发明人： Anwar Ali , Tauman T. Lau , Max M. Yeung
IPC分类号： H01L2500
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with a VDDio bus line disposed on a first layer of the integrated circuit. The VDDio bus line is disposed along a length, and has a first width transverse to the length. A VSSio bus line is dispose on a second layer of the integrated circuit. The VSSio bus line is disposed along the length and has a second width transverse to the length. The second width of the VSSio bus line substantially overlaps the first width of the VDDio bus line. An input output cell is disposed on a third layer of the integrated circuit. The first layer, the second layer, and the third layer are all different layers of the integrated circuit. The input output cell has a first transistor electrically connected to the VDDio bus line, and a second transistor electrically connected to the VSSio bus line. The first transistor and the second transistor are disposed along the length within the input output cell.
摘要翻译：具有布置在集成电路的第一层上的VDDio总线的集成电路。 VDDio总线沿着长度设置，并且具有横向于该长度的第一宽度。 VSSio总线布置在集成电路的第二层上。 VSSio总线沿着该长度设置并且具有横向于该长度的第二宽度。 VSSio总线的第二宽度基本上与VDDio总线的第一宽度重叠。输入输出单元设置在集成电路的第三层上。第一层，第二层和第三层都是集成电路的不同层。输入输出单元具有电连接到VDDio总线的第一晶体管和与VSSio总线电连接的第二晶体管。第一晶体管和第二晶体管沿着输入输出单元内的长度设置。

32. 发明授权

US06586961B2 Structure and method of repair of integrated circuits 失效
公开(公告)号：US06586961B2
公开(公告)日：2003-07-01
申请号：US09911344
申请日：2001-07-23
申请人： Philippe Chaisemartin
发明人： Philippe Chaisemartin
IPC分类号： H01L2500
CPC分类号： G11C29/80 , H01L23/525 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an integrated circuit, at least one portion of which includes at least one group of standby cells for possible connection to said portion of the integrated circuit by replacement connections, the length of which cannot exceed a predetermined value. The inputs and outputs of the standby cells are connected to metal standby tracks being disposed on the circuit such that any node of the circuit portion is distant by at most said predetermined value from any point on the tracks.

33. 发明授权

US06583649B2 Signal transmission apparatus for setting delay amount based on operational speed 失效
标题翻译：用于根据操作速度设定延迟量的信号传输装置
公开(公告)号：US06583649B2
公开(公告)日：2003-06-24
申请号：US09759348
申请日：2001-01-16
申请人： Takuji Nakamura
发明人： Takuji Nakamura
IPC分类号： H01L2500
CPC分类号： H04L25/085
摘要： A signal transmission apparatus is disclosed for setting delay amounts based on an operational speed. At least some of a plurality of rectangular wave signals transmitted in parallel are individually delayed by a plurality of signal delaying means for different time periods from one another in order to prevent the occurrence of noise. At this point, the delay time in the plurality of signal delaying means are set by time varying means based on the operational speed of a digital circuit which outputs digital data as the rectangular wave signals.
摘要翻译：公开了一种基于操作速度来设置延迟量的信号传输装置。并行发送的多个矩形波信号中的至少一部分被多个信号延迟装置单独地延迟，用于不同的时间间隔，以防止噪声的发生。此时，多个信号延迟装置中的延迟时间是基于输出数字数据作为矩形波信号的数字电路的操作速度由时变装置设定的。

34. 发明授权

US06501330B2 Signal processing semiconductor integrated circuit device 失效
标题翻译：信号处理半导体集成电路器件
公开(公告)号：US06501330B2
公开(公告)日：2002-12-31
申请号：US10087820
申请日：2002-03-05
申请人： Nobuhiro Kasa , Yoshiyasu Tashiro , Kazuaki Hori
发明人： Nobuhiro Kasa , Yoshiyasu Tashiro , Kazuaki Hori
IPC分类号： H01L2500
CPC分类号： H01L21/76264 , H01L27/0623 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit comprising a first circuit block including an oscillation circuit considered to be a noise generator and a second circuit block including circuits considered to be easily affected by a noise generated by the oscillation circuit, being most likely led to a malfunction are created on a single semiconductor substrate with the first and second circuit blocks separated from each other. To put it more concretely, the first and second circuit blocks are respectively created in a first island area and a second island area on the surface of the semiconductor substrate. The first and second island areas are each enclosed by an insulating isolation band. A low-resistance semiconductor area is created in a base area excluding locations occupied by active elements in the first and second island areas and is connected to a stable voltage terminal.
摘要翻译：一种半导体集成电路，包括包括被认为是噪声发生器的振荡电路的第一电路块和包括被认为容易受到由振荡电路产生的噪声影响的电路的第二电路块，最可能导致故障具有彼此分离的第一和第二电路块的单个半导体衬底。更具体地说，第一和第二电路块分别在半导体衬底的表面上的第一岛区和第二岛区中产生。第一和第二岛区均由绝缘隔离带包围。在基区域中产生低电阻半导体区域，不包括在第一岛区域和第二岛区域中的有源元件占据的位置，并且连接到稳定的电压端子。

35. 发明授权

US06483344B2 Interconnect circuitry for implementing logic functions in a field programmable gate array and method of operation 有权
标题翻译：用于实现现场可编程门阵列中的逻辑功能的互连电路和操作方法
公开(公告)号：US06483344B2
公开(公告)日：2002-11-19
申请号：US09773320
申请日：2001-01-31
申请人： Vidyabhusan Gupta
发明人： Vidyabhusan Gupta
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , G06F15/7867 , H03K19/1778
摘要： There is disclosed a field programmable gate array that performs in the interconnect matrix selected Boolean logic functions, such as OR gates and NOR gates, normally performed in the configurable logic blocks of the FPGA. The field programmable gate array comprises: 1) a plurality of configurable logic blocks (CLBs); 2) a plurality of interconnects; 3) a plurality of interconnect switches for coupling ones of the plurality of interconnects to each other and to inputs and outputs of the plurality of configurable logic blocks; and 4) an interconnect switch controller for controlling the plurality of interconnect switches. The interconnect switch controller in a first switch configuration causes a first interconnect to be coupled to an output of a first CLB, causes a second interconnect to be coupled to an output of a second CLB, causes the first and second interconnects to be coupled to a third interconnect, and causes the third interconnect to be coupled to a pull-up device coupled to a power supply source of the field programmable gate array. The first, second and third interconnects and the pull-up device thereby form a two-input OR gate.
摘要翻译：公开了一种现场可编程门阵列，其在互连矩阵中执行通常在FPGA的可配置逻辑块中执行的所选择的布尔逻辑功能，例如OR门和NOR门。现场可编程门阵列包括：1）多个可配置逻辑块（CLB）; 2）多个互连; 3）多个互连开关，用于将所述多个互连中的一个互连到所述多个可配置逻辑块的输入和输出; 以及4）用于控制所述多个互连开关的互连开关控制器。在第一开关配置中的互连开关控制器使得第一互连件耦合到第一CLB的输出端，使第二互连件耦合到第二CLB的输出，使第一和第二互连件耦合到第三互连，并且使第三互连耦合到耦合到现场可编程门阵列的电源的上拉器件。因此，第一，第二和第三互连和上拉器件形成双输入或门。

36. 发明授权

US06480059B2 Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances 失效
标题翻译：减少由制造工艺公差引起的I / O电路和时钟驱动器中的时序偏差的方法
公开(公告)号：US06480059B2
公开(公告)日：2002-11-12
申请号：US09473855
申请日：1999-12-28
申请人： Sanjay Dabral , Krishna Seshan
发明人： Sanjay Dabral , Krishna Seshan
IPC分类号： H01L2500
CPC分类号： H03L7/00 , G06F13/4072 , H01L21/823418 , H01L21/823437 , H01L21/823828 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.
摘要翻译：降低场效应晶体管器件中的随机处理引起的时序变化的方法包括提供具有有源区的半导体衬底，以及形成在有源区的一部分上具有栅极的晶体管，栅极具有第一支脚和第二条腿在另一方面，提出了一种改进严格匹配电路的定时偏移的方法。在本发明的另一方面，提出了一种场效应晶体管和集成电路器件，其可用于在存在随机制造或工艺引起的变化的情况下改善时序鲁棒性。

37. 发明授权

US06417692B2 Programmable I/O cells with multiple drivers 有权
标题翻译：具有多个驱动程序的可编程I / O单元
公开(公告)号：US06417692B2
公开(公告)日：2002-07-09
申请号：US09777393
申请日：2001-02-05
申请人： Eric M. Shiflet
发明人： Eric M. Shiflet
IPC分类号： H01L2500
CPC分类号： H03K19/17744 , H03K19/17788
摘要： A programmable input/output cell (I/O cell) for use with integrated circuits, and in particular programmable logic devices, is presented comprising input receiver circuitry, output driver circuitry and programmable elements. The input receiver and output driver circuitry each include multiple receivers/drivers that provide an interface between the signaling level of the integrated circuit and at least two other signaling standards. The programmable elements may be programmed to select a different signaling standard for each I/O cell to operate at, if desired. For instance, adjacent I/O cells may be connected to two different bus structures that utilize different signaling levels. The invention enables one I/O cell to translate between the PLD signaling level and the first bus signaling level, while the second I/O cell translates between the integrated circuit signaling level and the second bus signaling level.
摘要翻译：提供了用于集成电路，特别是可编程逻辑器件的可编程输入/输出单元（I / O单元），包括输入接收器电路，输出驱动器电路和可编程元件。输入接收器和输出驱动器电路各自包括多个接收器/驱动器，其提供集成电路的信号电平与至少两个其它信令标准之间的接口。如果需要，可编程元件可以被编程为为每个I / O单元选择不同的信号标准来操作。例如，相邻的I / O单元可以连接到利用不同信令级别的两个不同的总线结构。本发明使得一个I / O小区能够在PLD信令级别和第一总线信令级别之间转换，而第二I / O单元在集成电路信令级别和第二总线信令级别之间转换。

38. 发明授权

US06400182B2 Semiconductor integrated circuit device and method of laying out clock driver used in the semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件和布置在半导体集成电路器件中使用的时钟驱动器的方法
公开(公告)号：US06400182B2
公开(公告)日：2002-06-04
申请号：US09734880
申请日：2000-12-13
申请人： Nobuyuki Ikeda
发明人： Nobuyuki Ikeda
IPC分类号： H01L2500
CPC分类号： H01L27/0207 , H03K19/1735
摘要： In a semiconductor integrated circuit, the number of rows of transistors in each of first driver circuits is increased or decreased using MOS transistors group in clock driver circuits regions arranged in an array, such as in portions of circuit cell regions into which a core region is divided, in order to supply clock signals to cell, such as a megacell, through a mesh of interconnected clock signal supply lines, in the core region.
摘要翻译：在半导体集成电路中，使用以阵列布置的时钟驱动电路区域中的MOS晶体管组，例如在芯区域为其的电路单元区域的部分中，使第一驱动电路中的每一个中的晶体管的行数增加或减少分配，以便通过核心区域中的互连的时钟信号供应线的网格向诸如兆位的小区提供时钟信号。

39. 发明授权

US06384492B1 Power semiconductor packaging 失效
标题翻译：功率半导体封装
公开(公告)号：US06384492B1
公开(公告)日：2002-05-07
申请号：US09305555
申请日：1999-05-05
申请人： Arthur H. Iversen , George Gabor
发明人： Arthur H. Iversen , George Gabor
IPC分类号： H01L2500
CPC分类号： H01L23/467 , H01L24/48 , H01L24/49 , H01L25/07 , H01L25/112 , H01L25/162 , H01L25/165 , H01L2224/0603 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/49111 , H01L2924/00014 , H01L2924/01004 , H01L2924/01019 , H01L2924/01077 , H01L2924/1301 , H01L2924/13034 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/19041 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H02M7/003 , Y10T307/865 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Power output switching circuit for use in high current and high frequency applications. The output circuit provides a series of geometrically symmetric, parallel spaced semiconductor converters arranged such that the voltage for each semiconductor output device is substantially equal and minimal for each device. In this way, each device exhibits substantially the same impedance, such that circuit performance is largely a function of intrinsic device characteristics, and substantially independent of cross coupling and other external influences.
摘要翻译：电源输出开关电路用于大电流和高频应用。输出电路提供一系列几何对称的平行间隔的半导体转换器，其布置成使得每个半导体输出器件的电压对于每个器件基本上相同且最小。以这种方式，每个器件表现出基本上相同的阻抗，使得电路性能主要是本征器件特性的函数，并且基本上与交叉耦合和其它外部影响无关。

40. 发明授权

US06380479B2 Photovoltaic element and method for manufacture thereof 有权
标题翻译：光伏元件及其制造方法
公开(公告)号：US06380479B2
公开(公告)日：2002-04-30
申请号：US09813296
申请日：2001-03-21
申请人： Takuo Nakai , Hiroyuki Taniguchi , Teruhiko Ienaga , Yasuo Kadonaga
发明人： Takuo Nakai , Hiroyuki Taniguchi , Teruhiko Ienaga , Yasuo Kadonaga
IPC分类号： H01L2500
CPC分类号： H01L31/02363 , H01L31/035281 , H01L31/03529 , H01L31/0747 , Y02E10/50
摘要： A photovoltaic element which directly converts an optical energy such as solar light into an electric energy. After many uneven sections are formed on the surface of an n-type crystalline silicon substrate (1), the surface of the substrate (1) is isotropically etched. Then the bottoms (b) of the recessed sections are rounded and a p-type amorphous silicon layer (3) is formed on the surface of the substrate (1) through an intrinsic amorphous silicon layer (2). The shape of the surface of the substrate (1) after isotropic etching is such that the bottoms of the recessed sections are slightly rounded and therefore the amorphous silicon layer can be deposited in a uniform thickness.
摘要翻译：将诸如太阳光的光能直接转换成电能的光电元件。在n型晶体硅衬底（1）的表面上形成许多不平坦部分之后，对基片（1）的表面进行各向同性蚀刻。然后，凹部的底部（b）是圆形的，并且通过本征非晶硅层（2）在衬底（1）的表面上形成p型非晶硅层（3）。各向同性蚀刻后的基板（1）的表面的形状使得凹部的底部略微变圆，因此可以以均匀的厚度沉积非晶硅层。

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