专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明公开

EP0482845A3 Digital-to-analog converting unit with improved linearity 失效
标题翻译：数字模拟转换单元具有更高的线性度
公开(公告)号：EP0482845A3
公开(公告)日：1994-01-12
申请号：EP91309667.3
申请日：1991-10-18
申请人： NEC CORPORATION
发明人： Ogawara, Takeshi, c/o NEC Corporation
IPC分类号： H03M1/74
CPC分类号： H03M1/0651 , H03M1/685 , H03M1/747
摘要： A digital-to-analog converting unit decodes a digital input signal into a decoded signal, and selectively allows constant-current cells (C11 to C7m) arranged in matrix to supply unit currents for producing an analog output signal, wherein a decoding circuit (12b) incorporated in the digital-to-analog converting unit sequentially selects the constant-current cells in such a manner that insufficient increment of current produced by one of the constant-current-cells (C51) cancels out excessive increment of current produced by another constant-current cell (C31) so that the analog output signal is improved in linearity.
摘要翻译：数字 - 模拟转换单元将数字输入信号解码为解码信号，并且选择性地允许以矩阵排列的恒定电流单元（C11至C7m）提供用于产生模拟输出信号的单位电流，其中解码电路（12b ）以数字 - 模拟转换单元中的一个恒流单元（C51）产生的电流增量不足以抵消由另一常数产生的电流的过度增加的方式顺序选择恒流单元 - 电流单元（C31），以便模拟输出信号的线性度得到改善。

32. 发明授权

US09712183B2 Axially and centrally symmetric current source array 有权
公开(公告)号：US09712183B2
公开(公告)日：2017-07-18
申请号：US15160755
申请日：2016-05-20
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： Jade Deng , Keith Ma
IPC分类号： H03M1/06 , H03M1/68 , H03M1/74
CPC分类号： H03M1/68 , H03M1/0651 , H03M1/74 , H03M1/742
摘要： A current source device having a current source array includes a plurality of current source units, a plurality of least significant bits, and a plurality of most significant bits. The current source units are arranged along a plurality rows and columns of a current source array. Each of the least significant bits includes a first amount of current source units is placed at the geometric center of the current source array. Each of the most significant bits includes a second amount of current source units. The second amount is the first amount multiplied by a positive integer. The two adjacent bits in the most significant bits are centrally symmetrical to the geometric center.

33. 发明申请

US20170163280A1 AXIALLY AND CENTRALLY SYMMETRIC CURRENT SOURCE ARRAY 有权
公开(公告)号：US20170163280A1
公开(公告)日：2017-06-08
申请号：US15160755
申请日：2016-05-20
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： Jade DENG , Keith MA
IPC分类号： H03M1/68 , H03M1/74
CPC分类号： H03M1/68 , H03M1/0651 , H03M1/74 , H03M1/742
摘要： A current source device having a current source array includes a plurality of current source units, a plurality of least significant bits, and a plurality of most significant bits. The current source units are arranged along a plurality rows and columns of a current source array. Each of the least significant bits includes a first amount of current source units is placed at the geometric center of the current source array. Each of the most significant bits includes a second amount of current source units. The second amount is the first amount multiplied by a positive integer. The two adjacent bits in the most significant bits are centrally symmetrical to the geometric center.

34. 发明授权

US09515673B2 D/A conversion circuit, oscillator, electronic apparatus, and moving object 有权
标题翻译： D / A转换电路，振荡器，电子设备和移动物体
公开(公告)号：US09515673B2
公开(公告)日：2016-12-06
申请号：US14995473
申请日：2016-01-14
申请人： Seiko Epson Corporation
发明人： Shigenori Isozaki
IPC分类号： H03M1/66 , H01L27/06 , H01L49/02 , H01L27/02 , H01L29/49 , H01L27/092 , H03B5/02
CPC分类号： H03M1/66 , H01L27/0207 , H01L27/0629 , H01L27/092 , H01L28/20 , H01L29/4916 , H03B5/02 , H03B5/32 , H03M1/0651 , H03M1/72 , H03M1/76
摘要： A D/A conversion circuit includes a plurality of resistors that are connected to each other in series, and a plurality of MOS transistors that are connected to terminals of the plurality of resistors, respectively. The plurality of resistors and the plurality of MOS transistors are formed on a semiconductor substrate. Each of the plurality of resistors is constituted by a resistive element and a plurality of contacts provided in the resistive element. The plurality of MOS transistors are disposed so that a plurality of virtual straight lines that pass through each of the plurality of contacts and are perpendicular to a longitudinal direction of the resistive element pass between gate electrodes of two adjacent MOS transistors, when seen in a plan view of the semiconductor substrate.
摘要翻译： D / A转换电路包括彼此串联连接的多个电阻器和分别连接到多个电阻器的端子的多个MOS晶体管。多个电阻器和多个MOS晶体管形成在半导体衬底上。多个电阻器中的每一个由电阻元件和设置在电阻元件中的多个触点构成。多个MOS晶体管被配置为使得当在平面图中看到时，穿过多个触点中的每一个并且与电阻元件的纵向方向垂直的多个虚拟直线在两个相邻的MOS晶体管的栅电极之间通过半导体衬底的视图。

35. 发明授权

US06603417B2 CMOS DAC with high impedance differential current drivers 失效
公开(公告)号：US06603417B2
公开(公告)日：2003-08-05
申请号：US10124551
申请日：2002-04-17
申请人： David Vetea Greig
发明人： David Vetea Greig
IPC分类号： H03M166
CPC分类号： H03M1/0604 , H03M1/0651 , H03M1/685
摘要： High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance. Hierarchical gradient symmetry cancellation techniques are also employed to reduce integral non-linearity attributable to process-related surface gradients.

36. 发明授权

US06496131B2 Capacitor-array D/A converter including a thermometer decoder and a capacitor array 失效
标题翻译：电容阵列D / A转换器包括温度计解码器和电容器阵列
公开(公告)号：US06496131B2
公开(公告)日：2002-12-17
申请号：US09963063
申请日：2001-09-25
申请人： Chikashi Yoshinaga
发明人： Chikashi Yoshinaga
IPC分类号： H03M166
CPC分类号： H03M1/0651 , H03M1/687 , H03M1/806
摘要： In a capacitor-array D/A converter which includes a thermometer decoder (103) for thermometer-decoding a decoder input signal having first through m-th (m is an integer not less than two) input bits to produce an output signal having first through n-th (n=2m−1) output bits, where m is an integer not less than two and where n is equal to (2m−1), first through n-th switches (SU1 to SU31) corresponding to the first through the n-th output bits of the thermometer decoder, and a capacitor array (104) including first through n-th capacitors (8C1 through 8C31) corresponding to the first through the n-th switches, the first through the n-th capacitors are arranged in a main area of the capacitor array and in a row direction of the capacitor array consecutively from the center outward to the left and the right to be symmetrical. Each of the first through the n-th switches are supplied with a corresponding bit of the first through the n-th output bits from the thermometer decoder. The corresponding bit corresponds to each of the first through the n-th switches under consideration. Each of the first through the n-th switches operates so that, when the corresponding bit has a logic “1” level, a corresponding capacitor of the first through the n-th capacitors is applied with a predetermined voltage not equal to zero and that, when the corresponding bit has a logic “0” level, the corresponding capacitor is grounded. The corresponding capacitor corresponds to each of the first through the n-th switches.
摘要翻译：在一个电容阵列D / A转换器中，它包括一个温度计解码器（103），用于对第一至第m（m是不小于二的整数）的解码器输入信号进行温度计解码，以产生具有第一通过第n（n = 2m-1）个输出位，其中m是不小于2的整数，并且其中n等于（2m-1），第一到第n开关（SU1至SU31）对应于第一通过温度计解码器的第n个输出位以及包括与第一至第n开关相对应的第一至第n电容器（8C1至8C31）的电容器阵列（104），第一至第n电容器被布置在电容器阵列的主区域中，并且从电容器阵列的行方向连续地从中心向外向左和向右对称。第一至第n开关中的每一个被提供有来自温度计解码器的第一至第n输出位的相应位。对应的位对应于正在考虑的第一至第n开关中的每一个。第一至第n开关中的每一个操作使得当相应的位具有逻辑“1”电平时，第一至第n电容器的对应电容器以不等于零的预定电压被施加，并且，当相应位具有逻辑“0”电平时，相应的电容接地。对应的电容器对应于第一至第n开关中的每一个。

37. 发明授权

US6157333A Method for selecting a sequence of cells inside a bidimensional matrix structure of a digital-analog converter and corresponding converter 有权
标题翻译：用于选择数模转换器和相应转换器的二维矩阵结构内的单元格序列的方法
公开(公告)号：US6157333A
公开(公告)日：2000-12-05
申请号：US153983
申请日：1998-09-16
申请人： Filip Marcel Louagie , Zhong Yuan Chang , Jean-Philippe Robert Adiel Cornil
发明人： Filip Marcel Louagie , Zhong Yuan Chang , Jean-Philippe Robert Adiel Cornil
IPC分类号： H03M1/74 , H03M1/06 , H03M1/68 , H03M1/00
CPC分类号： H03M1/0651 , H03M1/685 , H03M1/747
摘要： The invention relates to a method for selecting a sequence of cells of current sources inside a cell matrix structure of a digital-analog converter and also to the corresponding converter. Symmetries are used with regard to the centre (C) of a rectangular or preferably square matrix structure, with regard to a symmetry point (S) located at a quarter of the length of a diagonal (D1) from the centre and with regard to one of the two mean perpendiculars (M1) of the structure for selecting the mapping areas (1, 2, . . . ) for the consecutive cells.
摘要翻译：本发明涉及一种用于选择数模转换器的单元矩阵结构内的电流源单元序列以及相应的转换器的方法。关于矩形或优选正方形矩阵结构的中心（C），就对称点（S）而言，对称性位于距离中心的对角线（D1）长度的四分之一处，并且关于一个用于选择连续小区的映射区域（1,2，...）的结构的两个平均垂直（M1）。

38. 发明授权

US5453743A Two-dimensional symmetric thermometer matrix decoder of digital/analog converter 失效
标题翻译：数字/模拟转换器的二维对称体温矩阵解码器
公开(公告)号：US5453743A
公开(公告)日：1995-09-26
申请号：US998049
申请日：1992-12-29
申请人： Ku-Chang Kang
发明人： Ku-Chang Kang
IPC分类号： H03M1/06 , H03M1/68 , H03M1/74 , H03M1/66
CPC分类号： H03M1/0651 , H03M1/685 , H03M1/747
摘要： A two-dimensional symmetric thermometer matrix decoder of digital/analog converter reduces an integral non-linearity error due to the current gradient of the current sources by making the current sources two-dimensional and symmetrical when selecting the current sources. Up until now, the number of current sources had to be smaller than a half the amount of the current that flows when one current source is activated, and the number of digital bits of a digital/analog converter that can be increased used to be limited because an integral non-linearity error value becomes larger as the number of the current sources increases. To solve such problems, the present invention activates a current source located in the center of the current source array, and then two current sources located on the right and the left side of the centrally located current source are activated. Also, for the rows which are a group of current sources, a centrally located row is activated first and then the rows located above and below are symmetrically activated so that the next current sources mutually offset the error with each other, thereby reducing an integral non-linearity error. By doing so, a converter with a higher-resolution can be manufactured.
摘要翻译：数字/模拟转换器的二维对称温度计矩阵解码器通过在选择电流源时使电流源二维和对称地减小由于电流源的电流梯度引起的积分非线性误差。到目前为止，电流源的数量必须小于当一个电流源被激活时流过的电流量的一半，并且可以增加的数字/模拟转换器的数字位数被限制因为随着电流源的数量增加，积分非线性误差值变大。为了解决这些问题，本发明激活位于电流源阵列的中心的电流源，然后激活位于中心位置的电流源的右侧和左侧的两个电流源。此外，对于作为一组电流源的行，首先激活位于中心的行，然后位于上下的行被对称地激活，使得下一个电流源彼此相互偏移误差，从而减少积分非线性误差通过这样做，可以制造具有更高分辨率的转换器。

39. 发明授权

US5057838A D/A converter having centered switching sequence and centered arrangement of converter segment groups 失效
标题翻译：具有中心切换序列的转换器和转换器部分组的中心布置
公开(公告)号：US5057838A
公开(公告)日：1991-10-15
申请号：US526904
申请日：1990-05-22
申请人： Kazuhiro Tsuji , Tetsuya Iida , Takayuki Satoh
发明人： Kazuhiro Tsuji , Tetsuya Iida , Takayuki Satoh
IPC分类号： H03M1/74 , H03M1/06 , H03M1/68 , H03M1/76
CPC分类号： H03M1/0651 , H03M1/685 , H03M1/765
摘要： A plurality of segment groups constituting a D/A converter, and decoders for decoding digital signals and selecting segments constituting the segment groups are arranged on a semiconductor chip. The segments constituting the plurality of segment groups are mingled and two-dimensionally arranged. The positions of the centers of gravity of the respective segment groups are substantially matched with the center of the arranged segments.

40. 发明授权

US10038452B2 Incremental preloading in an analog-to-digital converter 有权
公开(公告)号：US10038452B2
公开(公告)日：2018-07-31
申请号：US15649313
申请日：2017-07-13
申请人： Analog Devices, Inc.
发明人： Baozhen Chen , Edward C. Guthrie , Michael C. W. Coln , Mark D. Maddox
IPC分类号： H03M1/08 , H03M1/06 , H03M1/80
CPC分类号： H03M1/0836 , H03M1/0651 , H03M1/0863 , H03M1/14 , H03M1/466 , H03M1/68 , H03M1/804 , H03M1/806
摘要： During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式