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1. 发明公开

KR20180039537A 조건부 분기 예측기 인덱스를 생성하기 위해 명령어 블록 인출 어드레스 및 분기 패턴의 해싱에서 다수의 바이트 오프셋을 사용하는 분기 예측기 审中-公开
公开(公告)号：KR20180039537A
公开(公告)日：2018-04-18
申请号：KR20160159351
申请日：2016-11-28
申请人： VIA ALLIANCE SEMICONDUCTOR CO LTD
发明人： WANG XIAOLING , YANG MENGCHEN , CHEN GUOHUA
IPC分类号： G06F9/30
CPC分类号： G06F9/3806 , G06F9/3848 , G06F12/0875 , G06F2212/452
摘要： 분기예측기는명령어캐시의명령어바이트블록에액세스하도록이용가능한블록어드레스와, 명령어바이트블록내의제1/제2 바이트오프셋을구비한다. 해싱로직은블록어드레스와각각의제1/제2 바이트오프셋으로부터형성되는분기패턴과각각의제1/제2 어드레스를해싱하여각각의제1/제2 인덱스를생성한다. 조건부분기예측기는제1/제2 인덱스를수신하고이에응답하여명령어바이트블록에서제1/제2 조건부분기명령어의각각의제1/제2 방향예측을제공한다. 일실시예에서, 분기목표어드레스캐시(BTAC)는바이트오프셋을제공하고, 제1/제2 방향예측은 BTAC에의해또한제공되는제1/제2 목표어드레스와정적으로연관된다. 대안으로, 바이트오프셋은사전결정된값이고, 제1/제2 방향예측은 BTAC에의해제공되는바이트오프셋의상대크기를기초로하여제1/제2 목표어드레스와동적으로연관된다.

2. 发明申请

WO2016097802A1 MECHANISM TO PRECLUDE LOAD REPLAYS DEPENDENT ON LONG LOAD CYCLES IN AN OUT-ORDER PROCESSOR 审中-公开
标题翻译：预防在外部处理者中长期循环的依赖关系的机制
公开(公告)号：WO2016097802A1
公开(公告)日：2016-06-23
申请号：PCT/IB2014/003215
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： COL, Gerard, M. , EDDY, Colin , HENRY, G., Glenn
IPC分类号： G06F9/48
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/3855 , G06F9/5011 , G06F2209/507 , Y02D10/22
摘要： An apparatus includes first and second reservation stations. The first reservation station (421.L) dispatches a load micro instruction, and indicates on a hold bus (444) if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory, where the specified load instruction requires more than a first number of clock cycles to retrieve the operand. The second reservation station (421.1-421.N) is coupled to the hold bus (444), and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus (444) that the load micro instruction is the specified load micro instruction, the second reservation station (421.1-421.N) is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.
摘要翻译：一种装置包括第一和第二保留站。第一保留站（421.L）调度负载微指令，并且在保持总线（444）上指示负载微指令是否是指定的负载微指令，用于从除核心缓存之外的规定资源检索操作数存储器，其中指定的加载指令需要多于第一数量的时钟周期来检索操作数。第二保留站（421.1-421.N）被耦合到保持总线（444），并在其中分派一个或多个依赖于负载微指令执行的一个或多个较小的微指令，以在第一个加载微指令，并且如果在保持总线（444）上指示负载微指令是指定的负载微指令，则第二保留站（421.1-421.N）被配置为停止一个或多个更年轻的微指令，直到加载微指令已经检索到操作数。

3. 发明申请

WO2016097794A1 PREFETCHING WITH LEVEL OF AGGRESSIVENESS BASED ON EFFECTIVENESS BY MEMORY ACCESS TYPE 审中-公开
标题翻译：基于存储器访问类型的有效性预测具有等级
公开(公告)号：WO2016097794A1
公开(公告)日：2016-06-23
申请号：PCT/IB2014/003175
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： HOOKER, Rodney, E. , EDDY, Colin , REED, Douglas, R. , GREER, John, Michael
IPC分类号： G06F9/38
CPC分类号： G06F12/0862 , G06F8/4442 , G06F9/30043 , G06F9/3455 , G06F9/3802 , G06F9/383 , G06F11/30 , G06F12/0875 , G06F12/1009 , G06F12/127 , G06F2212/1024 , G06F2212/452 , G06F2212/502 , G06F2212/602 , G06F2212/6026 , Y02D10/13
摘要： A processor includes a prefetched 102) that prefetches data in response to memory accesses(134), wherein each memory access has an associated memory access type (MAT) of a plurality of predetermined MATs. The processor also includes a table(106) that holds scores that indicate effectiveness of the prefetcher to prefetch data with respect to the plurality of predetermined MATs. The prefetcher( 102) prefetches data in response to memory accesses at a level of aggressiveness based on the scores held in the table(106) and the associated MATs of the memory accesses.
摘要翻译：处理器包括预取存储器访问（134）的预取数据（102），其中每个存储器访问具有多个预定MAT的相关联的存储器访问类型（MAT）。处理器还包括表（106），其保存指示预取器相对于多个预定MAT预取数据的有效性的分数。预取器（102）基于保持在表（106）中的分数和存储器访问的相关联的MAT分级，以侵略性水平响应于存储器访问预取数据。

4. 发明申请

WO2016097792A1 APPARATUS AND METHOD TO PRECLUDE LOAD REPLAYS DEPENDENT ON WRITE COMBINING MEMORY SPACE ACCESS IN OUT-OF-ORDER PROCESSOR 审中-公开
标题翻译：根据订单处理程序中写入组合记忆空间访问依据的装载和方法
公开(公告)号：WO2016097792A1
公开(公告)日：2016-06-23
申请号：PCT/IB2014/003171
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： COL, Gerard, M. , EDDY, Colin , HENRY, G., Glenn
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3861
摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of prescribed resources includes system memory, coupled to the out-of-order processor via a memory bus, where the specified load micro instruction is known to resolve to write combining memory space in the system memory.
摘要翻译：一种包括第一和第二保留站的装置。第一保留站调度负载微指令，并且在保持总线上指示负载微指令是否是指定的从指定资源（除了内核高速缓冲存储器）检索操作数的指定负载微指令。第二保留站耦合到保持总线，并且在分配第一加载微指令之后的多个时钟周期之后，分派一个或多个取决于载入微指令以执行的较新的微指令，并且如果在所述保持总线，所述加载微指令是指定的负载微指令，所述第二保留站被配置为停止所述一个或多个较小的微指令的分派，直到所述加载微指令已经检索到所述操作数。多个规定资源包括经由存储器总线耦合到无序处理器的系统存储器，其中已知指定的负载微指令解决写入组合系统存储器中的存储器空间。

5. 发明申请

WO2016092346A1 CONDITIONAL PATTERN DETECTOR FOR DETECTING HANGS 审中-公开
标题翻译：用于检测HANGS的条件图案检测器
公开(公告)号：WO2016092346A1
公开(公告)日：2016-06-16
申请号：PCT/IB2014/003181
申请日：2014-12-13
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： HOOKER, Rodney, E. , REED, Douglas, R.
IPC分类号： G06F9/46
CPC分类号： G06F11/079 , G06F9/46 , G06F11/00 , G06F11/073 , G06F11/0751 , G06F11/0787 , G06F11/141 , G06F11/1451 , G06F11/1474 , G06F12/0855 , G06F2201/805 , G06F2201/84 , G06F2212/1041 , G06F2212/608
摘要： A microprocessor comprises a cache including a tag array; a tag pipeline that arbitrates access to the tag array; and a pattern detector. The pattern detector comprises snapshot capture logic that captures snapshots of tagpipe arbs— including information about whether the tagpipe arb is a load, snoop, store or other arb type and whether the tagpipe arb completed or replayed— and a plurality of configurable register modules operable to store user-configured snapshot patterns. Configuration logic enables a user to specify, for each configurable register module, properties of tagpipe arbs for the pattern detector to detect as well as dependencies between the configurable register modules. A register module becomes triggered if a tagpipe arb or pattern of tagpipe arbs meets the user-specified properties for the register module and if any other register module on which the register module depends is also in a triggered state.
摘要翻译：微处理器包括包括标签阵列的高速缓存器; 标记流水线，用于仲裁对标签数组的访问; 和图案检测器。模式检测器包括快照捕捉逻辑，其捕获标记箭头的快照，包括关于标记管道arb是否是加载，窥探，存储或其他arb类型以及标记管道arb是否完成或重放的信息，以及多个可配置寄存器模块可操作以存储用户配置的快照模式。配置逻辑使用户能够为每个可配置的寄存器模块指定用于模式检测器检测的标记框的属性以及可配置寄存器模块之间的依赖关系。如果标记管道arb或标记曲线模式满足用户指定的寄存器模块的属性，并且寄存器模块所依赖的任何其他寄存器模块也处于触发状态，则寄存器模块将被触发。

6. 发明申请

WO2015177592A1 PROGRAMMING APPARATUS AND METHOD FOR REPAIRING CACHE ARRAYS IN MULTI-CORE MICROPROCESSOR 审中-公开
标题翻译：用于修复多核微处理器中的高速缓存阵列的编程设备和方法
公开(公告)号：WO2015177592A1
公开(公告)日：2015-11-26
申请号：PCT/IB2014/003185
申请日：2014-12-12
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： HENRY, G., Glenn , JAIN, Dinesh, K. , GASKINS, Stephan
IPC分类号： G06F15/163
CPC分类号： G06F12/0893 , G06F1/3275 , G06F8/66 , G06F9/4403 , G06F12/0811 , G06F12/12 , G06F15/177 , G06F2212/222 , G06F2212/283 , G06F2212/601 , G11C7/20 , G11C17/16 , G11C17/18 , G11C2029/4402
摘要： An apparatus includes a programmer, a stores, and a plurality of cores. The programmer programs a fuse array with compressed configuration data. The stores provides for storage and access of decompressed configuration data sets. Each of a plurality of cores is coupled to the fuse array. One of the cores is accesses the fuse array upon power-up/reset to decompress and store decompressed configuration data sets for one or more cache memories. Each of the cores includes reset logic and sleep logic. The reset logic employs the decompressed configuration data sets to initialize the one or more cache memories upon power- up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following the power gating event.
摘要翻译：一种装置包括编程器，存储器和多个核心。编程器编程具有压缩配置数据的保险丝阵列。这些商店提供解压缩配置数据集的存储和访问。多个芯中的每一个耦合到熔丝阵列。其中一个内核在上电/复位时访问熔丝阵列，以解压缩并存储一个或多个缓存存储器的解压缩配置数据集。每个核心包括复位逻辑和睡眠逻辑。复位逻辑采用解压缩的配置数据集在上电/复位时初始化一个或多个高速缓冲存储器。休眠逻辑确定在电源门控事件之后恢复电力，随后访问商店以检索并使用解压缩的配置数据集来初始化电源门控事件之后的一个或多个高速缓存。

7. 发明申请

WO2016097793A1 MECHANISM TO PRECLUDE LOAD REPLAYS DEPENDENT ON OFF-DIE CONTROL ELEMENT ACCESS IN OUT-OF-ORDER PROCESSOR 审中-公开
标题翻译：机构预防负荷补偿依赖于外部控制元件访问超出处理器
公开(公告)号：WO2016097793A1
公开(公告)日：2016-06-23
申请号：PCT/IB2014/003173
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： COL, Gerard, M. , EDDY, Colin , GLENN, Henry, G.
IPC分类号： G06F15/163
CPC分类号： G06F9/3855 , G06F9/30043 , G06F9/3836 , G06F13/36 , Y02D10/14
摘要： An apparatus includes first and second reservation stations. The first reservation station (421.L) dispatches a load micro instruction, and indicates on a hold bus (444) if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station (421.1-421.N) is coupled to the hold bus (444), and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus (444) that the load micro instruction is the specified load micro instruction, the second reservation station (421.1-421.N) is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes a control element, coupled to the out-of order processor via a control bus.
摘要翻译：一种装置包括第一和第二保留站。第一保留站（421.L）调度负载微指令，并且在保持总线（444）上指示负载微指令是否是指定的负载微指令，用于从除核心缓存之外的规定资源检索操作数记忆。第二保留站（421.1-421.N）被耦合到保持总线（444），并在其中分派一个或多个依赖于负载微指令执行的一个或多个较小的微指令，以在第一个加载微指令，并且如果在保持总线（444）上指示负载微指令是指定的负载微指令，则第二保留站（421.1-421.N）被配置为停止一个或多个更年轻的微指令，直到加载微指令已经检索到操作数。多个非核心资源包括经由控制总线耦合到失序处理器的控制元件。

8. 发明申请

WO2016012831A1 SIMULTANEOUS INVALIDATION OF ALL ADDRESS TRANSLATION CACHE ENTRIES ASSOCIATED WITH X86 PROCESS CONTEXT IDENTIFIER 审中-公开
标题翻译：与X86过程相关的所有地址翻译高速缓存的同时失效语境标识符
公开(公告)号：WO2016012831A1
公开(公告)日：2016-01-28
申请号：PCT/IB2014/003110
申请日：2014-11-26
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： EDDY, Colin
IPC分类号： G06F12/00
CPC分类号： G06F12/0891 , G06F12/1027 , G06F12/1036 , G06F12/1063 , G06F12/109 , G06F15/7839 , G06F2212/1016 , G06F2212/1044 , G06F2212/683
摘要： A translation-lookaside buffer (TLB) includes a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a local valid bit vector, wherein each bit of the local valid bit vector is mapped from a different value of an x86 instruction set architecture (ISA) process context identifier (PCID). The TLB also includes an input that receives an invalidation bit vector having bits corresponding to the bits of the local valid bit vector of the plurality of entries. The TLB also includes logic that simultaneously invalidates a bit of the local valid bit vector of each entry of the plurality of entries that corresponds to a set bit of the invalidation bit vector.
摘要翻译：翻译后备缓冲器（TLB）包括多个条目，其中多个条目的每个条目被配置为保存地址转换和本地有效位向量，其中本地有效位向量的每个位从不同的 x86指令集架构（ISA）进程上下文标识符（PCID）的值。 TLB还包括接收具有与多个条目的本地有效位向量的位对应的位的无效位向量的输入。 TLB还包括同时使对应于无效位向量的设置位的多个条目的每个条目的本地有效位向量的位的同时无效的逻辑。

9. 发明申请

WO2016012830A1 EFFICIENT ADDRESS TRANSLATION CACHING IN PROCESSOR THAT SUPPORTS LARGE NUMBER OF DIFFERENT ADDRESS SPACES 审中-公开
标题翻译：支持大量不同地址空间的处理器中的高效地址转换
公开(公告)号：WO2016012830A1
公开(公告)日：2016-01-28
申请号：PCT/IB2014/003084
申请日：2014-11-26
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： PARKS, Terry , EDDY, Colin , MOHAN, Viswanath , BUNDA, John, D.
IPC分类号： G06F12/10
CPC分类号： G06F12/0891 , G06F12/1027 , G06F12/1036 , G06F12/1063 , G06F12/109 , G06F15/7839 , G06F2212/1016 , G06F2212/1044 , G06F2212/683
摘要： A processor includes translation-lookaside buffer (TLB) (206) and a mapping module (204). The TLB (206) includes a plurality of entries (300), wherein each entry of the plurality of entries (300) is configured to hold an address translation (306, 308) and a valid bit vector (302, 304), wherein each bit of the valid bit vector (302, 304) indicates, for a respective address translation context, the address translation (306, 308) is valid if set and invalid if clear. The TLB (206) also includes an invalidation bit vector (302, 304) having bits corresponding to the bits of the valid bit vector (302, 304) of the plurality of entries (300), wherein a set bit of the invalidation bit vector (302, 304) indicates to simultaneously clear the corresponding bit of the valid bit vector (302, 304) of each entry of the plurality of entries (300). The mapping module (204) generates the invalidation bit vector (302, 304).
摘要翻译：处理器包括翻译后备缓冲器（TLB）（206）和映射模块（204）。 TLB（206）包括多个条目（300），其中多个条目（300）的每个条目被配置为保存地址转换（306,308）和有效位向量（302,304），其中每个条目对于相应的地址转换上下文，有效位向量（302,304）的位指示如果设置为无效，则地址转换（306,308）是有效的。 TLB（206）还包括具有对应于多个条目（300）的有效位向量（302,304）的比特的比特的无效比特向量（302,304），其中无效比特向量的设置比特（302,304）指示同时清除多个条目（300）的每个条目的有效位向量（302,304）的对应位。映射模块（204）生成无效位向量（302,304）。

10. 发明申请

WO2015177596A1 MULTI-CORE MICROPROCESSOR POWER GATING CACHE RESTORAL PROGRAMMING MECHANISM 审中-公开
标题翻译：多核心微处理器功率增益缓存缓存编程机制
公开(公告)号：WO2015177596A1
公开(公告)日：2015-11-26
申请号：PCT/IB2014/003267
申请日：2014-12-12
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： HENRY, G., Glenn , JAIN, Dinesh, K. , GASKINS, Stephan
IPC分类号： G11C15/04
CPC分类号： G06F12/0893 , G06F1/3275 , G06F8/66 , G06F9/4403 , G06F12/0811 , G06F12/12 , G06F15/177 , G06F2212/222 , G06F2212/283 , G06F2212/601 , G11C7/20 , G11C17/16 , G11C17/18 , G11C2029/4402
摘要： An apparatus includes a device programmer and a stores. The device programmer programs a semiconductor fuse array with compressed configuration data for a plurality of cores disposed on a die. The stores includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores is configured to access the semiconductor fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores, and where, following a power gating event, one of the each of the plurality of cores subsequently accesses a corresponding one of the each of the plurality of sub- stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches.
摘要翻译：一种装置包括装置编程器和商店。器件编程器针对设置在管芯上的多个核心编程具有压缩配置数据的半导体熔丝阵列。存储器包括多个子存储器，每个子存储器对应于多个核心中的每一个，其中多个核心中的一个核心被配置为在上电/复位时访问半导体熔丝阵列以读取和解压缩压缩的配置数据，并且存储多个子存储器中的多个核心内的一个或多个高速缓存存储器的多个解压缩配置数据集，并且其中，在电源门控事件之后，所述多个核心中的每一个之一随后访问多个子存储中的每个子存储器中的相应一个，以检索和使用解压缩的配置数据集来初始化一个或多个高速缓存。

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