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1. 发明申请

US20190081636A1 Method of Performing Analog-to-Digital Conversion 审中-公开
公开(公告)号：US20190081636A1
公开(公告)日：2019-03-14
申请号：US16040140
申请日：2018-07-19
申请人： Analog Devices, Inc.
发明人： Baozhen Chen , Lalinda D. Fernando , Zhichao Tan
IPC分类号： H03M1/46
CPC分类号： H03M1/468 , H03M1/002 , H03M1/462
摘要： A method of performing analog-to-digital conversion using a successive approximation (SAR) analog-to-digital converter (ADC). A previous digital output is compared to a range based on the first M bits of the previous digital output. If the previous digital output is within that range, a digital-to-analog converter (DAC) of the SAR ADC is preloaded with the first M bits of the previous digital output, prior to commencing bit trials. If the previous digital output is outside of that range, an offset is applied to the first M bits of the previous digital output and the DAC is preloaded based on the M bits and the offset, prior to performing bit trials. This method reduces the possibility of the next input being outside of a further range defined by the preload.

2. 发明授权

US10038452B2 Incremental preloading in an analog-to-digital converter 有权
公开(公告)号：US10038452B2
公开(公告)日：2018-07-31
申请号：US15649313
申请日：2017-07-13
申请人： Analog Devices, Inc.
发明人： Baozhen Chen , Edward C. Guthrie , Michael C. W. Coln , Mark D. Maddox
IPC分类号： H03M1/08 , H03M1/06 , H03M1/80
CPC分类号： H03M1/0836 , H03M1/0651 , H03M1/0863 , H03M1/14 , H03M1/466 , H03M1/68 , H03M1/804 , H03M1/806
摘要： During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.

3. 发明申请

US20180091165A1 INCREMENTAL PRELOADING IN AN ANALOG-TO-DIGITAL CONVERTER 审中-公开
公开(公告)号：US20180091165A1
公开(公告)日：2018-03-29
申请号：US15649313
申请日：2017-07-13
申请人： Analog Devices, Inc.
发明人： Baozhen Chen , Edward C. Guthrie , Michael C.W. Coln , Mark D. Maddox
IPC分类号： H03M1/08
CPC分类号： H03M1/0836 , H03M1/0651 , H03M1/0863 , H03M1/14 , H03M1/466 , H03M1/68 , H03M1/804 , H03M1/806
摘要： During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.

4. 发明授权

US09641189B2 Calibration techniques for SAR ADCs with on-chip reservoir capacitors 有权
公开(公告)号：US09641189B2
公开(公告)日：2017-05-02
申请号：US14747071
申请日：2015-06-23
申请人： ANALOG DEVICES, INC.
发明人： Mark D. Maddox , Michael Coln , Gary R. Carreau , Baozhen Chen
IPC分类号： H03M1/12 , H03M1/10 , H03M1/46
CPC分类号： H03M1/1071 , H03M1/1038 , H03M1/462 , H03M1/468
摘要： When reservoir capacitors are moved on-chip for individual bit decisions, a successive approximation register analog-to-digital converter (SAR ADC) has an addition source of error which can significantly affect the performance of the SAR ADC. Calibration techniques can be applied to measure and correct for such error in an SAR ADC using decide-and-set switching. Specifically, a calibration technique can expose the effective bit weight of each bit under test using a plurality of special input voltages and storing a calibration word for each bit under test to correct for the error. Such a calibration technique can lessen the need to store a calibration word for each possible output word to correct the additional source of error. Furthermore, another calibration technique can expose the effective bit weight of each bit under test without having to generate the plurality of special input voltages.

5. 发明授权

US10404264B2 Method of performing analog-to-digital conversion 有权
公开(公告)号：US10404264B2
公开(公告)日：2019-09-03
申请号：US16040140
申请日：2018-07-19
申请人： Analog Devices, Inc.
发明人： Baozhen Chen , Lalinda D. Fernando , Zhichao Tan
IPC分类号： H03M1/46 , H03M1/00
摘要： A method of performing analog-to-digital conversion using a successive approximation (SAR) analog-to-digital converter (ADC). A previous digital output is compared to a range based on the first M bits of the previous digital output. If the previous digital output is within that range, a digital-to-analog converter (DAC) of the SAR ADC is preloaded with the first M bits of the previous digital output, prior to commencing bit trials. If the previous digital output is outside of that range, an offset is applied to the first M bits of the previous digital output and the DAC is preloaded based on the M bits and the offset, prior to performing bit trials. This method reduces the possibility of the next input being outside of a further range defined by the preload.

6. 发明授权

US09553599B1 Techniques for reducing offsets in an analog to digital converter 有权
标题翻译：减少模数转换器偏移的技术
公开(公告)号：US09553599B1
公开(公告)日：2017-01-24
申请号：US15017995
申请日：2016-02-08
申请人： Analog Devices, Inc.
发明人： Baozhen Chen , Lalinda D. Fernando
IPC分类号： H03M1/06 , H03M1/46 , H03M1/20 , H03M1/42
CPC分类号： H03M1/1061 , H03M1/069 , H03M1/1033 , H03M1/14 , H03M1/468
摘要： In an example, a successive approximation register analog-to-digital converter includes a switched capacitor digital-to-analog converter (DAC) first array to sample an input signal and to convert a sample of the input signal to a digital value represented by a plurality of bits, the first array including a first group of capacitors representing at least some of the plurality of bits, a switched capacitor DAC second array including a second group of capacitors representing at least some of the plurality of bits, wherein at least one bit of the plurality of bits represented by the second group of capacitors is represented by at least two capacitors, and wherein each of the two capacitors is configured to be selectively connected to a selected one of at least two reference potentials such that the at least one bit represented by the second group of capacitors is switchable between at least three states.
摘要翻译：在一个示例中，逐次逼近寄存器模数转换器包括开关电容器数模转换器（DAC）第一阵列以对输入信号进行采样并将输入信号的采样转换为由多个位，所述第一阵列包括表示所述多个位中的至少一些位的第一组电容器;开关电容器DAC第二阵列，包括表示所述多个位中的至少一些位的第二组电容器，其中至少一个位由第二组电容器表示的多个位表示为至少两个电容器，并且其中两个电容器中的每一个被配置为选择性地连接到至少两个参考电位中的所选择的一个，使得至少一个位由第二组电容器表示，可在至少三种状态之间切换。

7. 发明授权

US10692967B1 High density self-routing metal-oxide-metal capacitor 有权
公开(公告)号：US10692967B1
公开(公告)日：2020-06-23
申请号：US16209768
申请日：2018-12-04
申请人： Analog Devices, Inc.
发明人： Baozhen Chen , Lalinda D. Fernando , Micah Galletta O'Halloran , Andrew Wayne Shaw
IPC分类号： H01L49/02 , H01L27/02
摘要： A self-routing capacitor for an integrated circuit having: a first electrode comprising a first base region and a first finger, the first finger extending from a wall of the first base region in a first direction; a second electrode comprising a second base region and a second finger; the second finger extending from a wall of the second base region in a second direction substantially parallel to and opposing the first direction, the second finger coupled to the first finger; a third electrode comprising a third base region and a third finger, the third finger extending from a first wall of the third base in the second direction; and a fourth electrode comprising a fourth finger, the fourth finger extending from a second wall of the third base region in the first direction. The capacitor being coupled to other metal layers through a base region of an electrode.

8. 发明授权

US09712181B1 Incremental preloading in an analog-to-digital converter 有权
公开(公告)号：US09712181B1
公开(公告)日：2017-07-18
申请号：US15273967
申请日：2016-09-23
申请人： Analog Devices, Inc.
发明人： Baozhen Chen , Edward C. Guthrie , Michael C. W. Coln , Mark D. Maddox
IPC分类号： H03M1/46 , H03M1/80 , H03M1/68 , H03M1/12
CPC分类号： H03M1/466 , H03M1/0863 , H03M1/1245 , H03M1/14 , H03M1/68 , H03M1/804 , H03M1/806
摘要： During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.

9. 发明申请

US20200176555A1 HIGH DENSITY SELF-ROUTING METAL-OXIDE-METAL CAPACITOR 审中-公开
公开(公告)号：US20200176555A1
公开(公告)日：2020-06-04
申请号：US16209768
申请日：2018-12-04
申请人： Analog Devices, Inc.
发明人： Baozhen Chen , Lalinda D. Fernando , Micah Galletta O'Halloran , Andrew Wayne Shaw
IPC分类号： H01L49/02 , H01L27/02
摘要： A self-routing capacitor for an integrated circuit having: a first electrode comprising a first base region and a first finger, the first finger extending from a wall of the first base region in a first direction; a second electrode comprising a second base region and a second finger, the second finger extending from a wall of the second base region in a second direction substantially parallel to and opposing the first direction, the second finger coupled to the first finger; a third electrode comprising a third base region and a third finger, the third finger extending from a first wall of the third base in the second direction; and a fourth electrode comprising a fourth finger, the fourth finger extending from a second wall of the third base region in the first direction. The capacitor being coupled to other metal layers through a base region of an electrode.

10. 发明授权

US09923569B1 Self-adaptive analog-to-digital converter 有权
公开(公告)号：US09923569B1
公开(公告)日：2018-03-20
申请号：US15700957
申请日：2017-09-11
申请人： Analog Devices, Inc.
发明人： Baozhen Chen , Lalinda D. Fernando , Frank M. Yaul
IPC分类号： H03M1/10 , H03M1/00
CPC分类号： H03M1/10 , H03M1/00 , H03M1/002 , H03M1/185 , H03M1/462
摘要： A self-adaptive SAR ADC techniques that can increase speed and/or decrease its power consumption. In some example approaches, one or more bits from a conversion of a previous sample of an analog input signal can be preloaded onto a DAC circuit of the ADC. If the preloaded bits are determined to be acceptable, bit trials on the current sample can be performed to determine the remaining bits. If not acceptable, the ADC can discard the preloaded bits and perform bit trials on all of the bits. The self-adaptive SAR ADC can include a control loop to adjust, e.g., increase or decrease, the number of bits that are preloaded in a subsequent bit trial using historical data.

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