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31. 发明授权

US6101148A Dynamic random access memory 失效
标题翻译：动态随机存取存储器
公开(公告)号：US6101148A
公开(公告)日：2000-08-08
申请号：US907019
申请日：1997-08-06
申请人： Junichi Okamura , Tohru Furuyama
发明人： Junichi Okamura , Tohru Furuyama
IPC分类号： G01R31/28 , G01R31/30 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/06 , G11C29/34 , G11C29/50 , H01L21/66 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C8/00
CPC分类号： G11C11/4085 , G11C11/4087 , G11C29/50 , G11C8/12 , G11C11/401
摘要： A dynamic random access memory includes a dynamic memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the dynamic memory cell, and a word line driving voltage source, to which power voltage is input for raising the input power voltage to generate a word line driving voltage. Also, the dynamic random access memory includes an address circuit for generating internal address signals in accordance with externally input address signals, a word line selecting circuit for decoding the internal address signals and outputting a word line selecting signal which varies within a range between the word line driving voltage and a ground potential, and a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, the word line driving circuit being provided in correspondence with the word line and having a P-channel MOS transistor which has a source connected to a first node having the word line driving voltage, a drain connected to the word line and a gate to which the word line selecting signal is applied.
摘要翻译：动态随机存取存储器包括具有传输N沟道MOS晶体管的动态存储单元和用于存储连接到传输N沟道MOS晶体管的数据的电容元件，连接到传输N沟道的栅极的字线晶体管，以及字线驱动电压源，输入电源电压以提高输入电源电压以产生字线驱动电压。此外，动态随机存取存储器包括用于根据外部输入的地址信号产生内部地址信号的地址电路，用于对内部地址信号进行解码的字线选择电路，并输出在字之间的范围内变化的字线选择信号线驱动电压和接地电位，以及用于根据字线选择信号驱动相应字线的字线驱动电路，字线驱动电路与字线对应地设置，并具有P沟道MOS晶体管其源极连接到具有字线驱动电压的第一节点，连接到字线的漏极和施加了字线选择信号的栅极。

32. 发明授权

US5754481A Clock synchronous type DRAM with latch 失效
标题翻译：时钟同步型DRAM带锁存器
公开(公告)号：US5754481A
公开(公告)日：1998-05-19
申请号：US857559
申请日：1997-05-16
申请人： Tomoaki Yabe , Kenji Numata , Katsuhiko Sato , Ryo Haga , Shinji Miyano , Tohru Furuyama
发明人： Tomoaki Yabe , Kenji Numata , Katsuhiko Sato , Ryo Haga , Shinji Miyano , Tohru Furuyama
IPC分类号： G11C7/10 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1072 , G11C7/1078
摘要： A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate. The write circuit writes data into the data latch in synchronism with a clock signal. At the time of writing data into the memory cells, data is previously supplied to the data latch by the write circuit and latched in the data latch, and after the transfer gate control circuit controls the transfer gate to supply data to the bit line pairs from the data latch, the sense amplifier control circuit activates the sense amplifier.
摘要翻译：半导体存储器件包括存储单元阵列，行解码器，位线对，读出放大器，读出放大器控制电路，数据锁存器，传输门，传输门控制电路和写电路。存储单元阵列具有以阵列形式排列的动态存储单元。行解码器解码行地址信号以选择存储单元阵列的所需行中的一行。每个位线对连接到布置在存储单元阵列的相应列上的存储单元的每一个。读出放大器放大在配对位线上读出的数据，并将数据反馈给配对的位线以保存数据。读出放大器控制电路控制读出放大器的工作。数据锁存器锁存读出数据和写入数据。传输门在数据锁存器和读出放大器之间传送数据。传输门控制电路控制传输门。写入电路与时钟信号同步地将数据写入数据锁存器。在将数据写入存储器单元时，数据预先由写入电路提供给数据锁存器并锁存在数据锁存器中，并且在传输门控制电路控制传输门以向位线对提供数据之后数据锁存器，读出放大器控制电路激活读出放大器。

33. 发明授权

US5525820A Semiconductor memory cell 失效
标题翻译：半导体存储单元
公开(公告)号：US5525820A
公开(公告)日：1996-06-11
申请号：US284274
申请日：1994-08-02
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： G11C11/405 , G11C11/404 , H01L21/8242 , H01L27/108
CPC分类号： G11C11/404
摘要： A semiconductor memory cell of the present invention comprises a cascade gate including a plurality of cascade-connected MOS transistors and having one end connected to a read/write node, and a plurality of capacitors for information storage connected at one end to said MOS transistors, respectively, at the end remote from said node.
摘要翻译：本发明的半导体存储单元包括：级联栅极，包括多个级联连接的MOS晶体管，并且一端连接到读/写节点;以及多个用于信息存储的电容器，其一端连接到所述MOS晶体管，分别在远离所述节点的末端。

34. 发明授权

US5479370A Semiconductor memory with bypass circuit 失效
标题翻译：带旁路电路的半导体存储器
公开(公告)号：US5479370A
公开(公告)日：1995-12-26
申请号：US376439
申请日：1995-01-23
申请人： Tohru Furuyama , Donald C. Stark
发明人： Tohru Furuyama , Donald C. Stark
IPC分类号： G11C11/401 , G11C8/04 , G11C11/405 , G11C29/00 , G11C29/04 , G11C13/00 , G11C11/34
CPC分类号： G11C8/04
摘要： A semiconductor memory of this invention comprises a memory cell array containing memory cells arranged in matrix form, word lines each connected to all the memory cells in the same row, and bit lines each connected to all the memory cells in the same column, a shift register containing a plurality of stages of shift circuits which is used as a serial address pointer for serially specifying the addresses of actually used rows and/or columns in the memory cell array, a bypass circuit capable of forming a bypass for the shift circuit at a given stage of the shift register, and a bypass control circuit for determining whether or not a bypass is to be formed by the bypass circuit.
摘要翻译：本发明的半导体存储器包括存储单元阵列，该存储单元阵列包含以矩阵形式布置的存储单元，每行连接到同一行中的所有存储单元的字线以及连接到同一列中的所有存储单元的位线，寄存器，其包含用于串行地指定存储单元阵列中的实际使用的行和/或列的地址的串行地址指针的多级移位电路，能够在一个位置上形成用于移位电路的旁路的旁路电路移位寄存器的给定级，以及用于判断旁路是否由旁路电路形成的旁路控制电路。

35. 发明授权

US5410512A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5410512A
公开(公告)日：1995-04-25
申请号：US64438
申请日：1993-05-21
申请人： Satoru Takase , Tohru Furuyama , Donald C. Stark , Natsuki Kushiyama , Kiyofumi Sakurai , Hiroyuki Noji , Shigeo Ohshima
发明人： Satoru Takase , Tohru Furuyama , Donald C. Stark , Natsuki Kushiyama , Kiyofumi Sakurai , Hiroyuki Noji , Shigeo Ohshima
IPC分类号： G11C11/401 , G06F12/02 , G11C7/00 , G11C7/10 , G11C11/407 , G11C11/41
CPC分类号： G11C7/1021
摘要： A semiconductor memory device includes a silicon chip and sub-arrays formed in the chip. In each of the sub-arrays, memory cells arranged in a matrix form, word lines provided for respective rows of each of the sub-arrays, and bit lines provided for respective columns of each of the sub-arrays are arranged. Further, in the chip, amplifier groups for amplifying data read out from the memory cells are arranged for the respective sub-arrays. Amplifiers connected to respective bit lines are provided in the amplifier groups and the amplifiers each have a function of continuously holding data read out from the memory cell.
摘要翻译：半导体存储器件包括形成在芯片中的硅芯片和子阵列。在每个子阵列中，布置成矩阵形式的存储器单元，为每个子阵列的各行提供的字线，以及为每个子阵列的各列提供的位线。此外，在芯片中，放置用于放大从存储单元读出的数据的放大器组用于各个子阵列。连接到相应位线的放大器设置在放大器组中，并且放大器各自具有连续保持从存储单元读出的数据的功能。

36. 发明授权

US5294776A Method of burning in a semiconductor device 失效
标题翻译：在半导体器件中燃烧的方法
公开(公告)号：US5294776A
公开(公告)日：1994-03-15
申请号：US926432
申请日：1992-08-10
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： H01L21/66 , G01R31/28 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , H01L21/768 , H01L21/8242 , H01L23/528 , H01L27/108 , G01R31/00
CPC分类号： G01R31/2856 , H01L21/76886 , H01L23/528 , G01R31/2831 , G01R31/2863 , H01L2924/0002
摘要： Since the power-supply and/or signal-transmission wiring layers connected to the semiconductor chip regions are formed, each individual integrated circuit can be burned in on the semiconductor wafer and, in other words, an integrated circuit can be burned in on a wafer level. The integrated circuit can thus be burned in at the end of a wafer process. An assembled semiconductor device is subjected to a high temperature or a high humidity, for checking the reliability of the assembled device.
摘要翻译：由于形成了连接到半导体芯片区域的电源和/或信号传输布线层，所以可以在半导体晶片上烧录各个集成电路，换句话说，集成电路可以在晶圆上燃烧水平。因此，集成电路可以在晶圆工艺结束时燃烧。组装的半导体器件经受高温或高湿度，用于检查组装的器件的可靠性。

37. 发明授权

US4841483A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US4841483A
公开(公告)日：1989-06-20
申请号：US130568
申请日：1987-12-09
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： G11C7/18 , G11C11/56
CPC分类号： G11C7/18 , G11C11/565 , G11C16/24
摘要： The invention provides a semiconductor memory having a plurality of memory cells and a bit line connected to the memory cells comprising, the bit line being formed of a plurality of sub-bit lines, switch means for interconnecting and disconnecting the sub-bit lines, reference potential means for storing reference potentials, and sense amplifier means for comparing the output of an addressed memory cell with the reference potentials, whereby the memory is capable of storing n-valued data using n different storage potentials.

38. 发明授权

US4733374A Dynamic semiconductor memory device 失效
标题翻译：动态半导体存储器件
公开(公告)号：US4733374A
公开(公告)日：1988-03-22
申请号：US844626
申请日：1986-03-27
申请人： Tohru Furuyama , Shigeyoshi Watanabe , Tatsuo Ikawa
发明人： Tohru Furuyama , Shigeyoshi Watanabe , Tatsuo Ikawa
IPC分类号： H01L27/108 , G11C8/14 , G11C11/408 , G11C11/4097 , G11C7/00
CPC分类号： G11C8/14 , G11C11/408 , G11C11/4097
摘要： A semiconductor memory device has N sense amplifiers each having first and second input terminals, N first memory cells, N second memory cells, N first bit lines each of which is connected to the first memory cells of the same column and connected to the first input terminal of one of the sense amplifiers, and N second bit lines each of which is connected to the second memory cells of the same column and connected to the second input terminal of one of the sense amplifiers. The first memory cells are formed in a first memory cell area and the second memory cells are formed in a second memory cell area arranged adjacent to the first memory cell area and on the same side as the first memory cell area with respect to the sense amplifiers.
摘要翻译：半导体存储器件具有N个读出放大器，每个读出放大器具有第一和第二输入端，N个第一存储单元，N个第二存储器单元，N个第一位线，每个第一位线连接到同一列的第一存储器单元并连接到第一输入端一个读出放大器的一个端子，以及N个第二位线，每个第二位线连接到同一列的第二存储器单元并连接到一个读出放大器的第二输入端。第一存储器单元形成在第一存储单元区域中，并且第二存储器单元形成在与第一存储单元区域相邻布置的第二存储器单元区域中，并且与第一存储器单元区域相对于读出放大器。

39. 发明授权

US4368529A Semiconductor memory circuit 失效
标题翻译：半导体存储电路
公开(公告)号：US4368529A
公开(公告)日：1983-01-11
申请号：US197950
申请日：1980-10-17
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： G11C11/409 , G11C11/4094 , G11C11/40
CPC分类号： G11C11/4094
摘要： A semiconductor matrix circuit includes first and second matrix arrays of semiconductor memory cells, a plurality of sense amplifiers each having a flip-flop circuit, a plurality of first bit lines each commonly connected to memory cells in the same row of the first matrix array and also connected respectively to first bi-stable output terminals of the flip-flop circuits, and a plurality of second bit lines each commonly connected to memory cells in the same row of the second matrix array and also connected respectively to second bi-stable output terminals of the flip-flop circuits. Switching MOS transistors are each connected between the first and second bi-stable output terminals of a corresponding one of the flip-flop circuits. After a reading operation, the first and second bit lines are selectively set to high and low potential levels V.sub.D and V.sub.S, and subsequently all the switching MOS transistors are rendered conductive to set the potential on all the bit lines to an intermediate level (V.sub.D +V.sub.S)/2.
摘要翻译：半导体矩阵电路包括半导体存储单元的第一和第二矩阵阵列，多个读出放大器，每个具有触发器电路，多个第一位线，每个第一位线共同连接到第一矩阵阵列的同一行中的存储器单元;以及还分别连接到触发器电路的第一双稳态输出端子，以及多个第二位线，每个第二位线共同连接到第二矩阵阵列的同一行中的存储器单元，并且还分别连接到第二双稳态输出端子的触发器电路。开关MOS晶体管分别连接在相应的一个触发器电路的第一和第二双稳态输出端子之间。在读取操作之后，第一和第二位线被选择性地设置为高电平和低电位电平VD和VS，随后所有开关MOS晶体管导通，以将所有位线上的电位设置为中间电平（VD + VS）/ 2。

40. 发明授权

US06381186B1 Dynamic random access memory 失效
标题翻译：动态随机存取存储器
公开(公告)号：US06381186B1
公开(公告)日：2002-04-30
申请号：US09939586
申请日：2001-08-28
申请人： Junichi Okamura , Tohru Furuyama
发明人： Junichi Okamura , Tohru Furuyama
IPC分类号： G11C700
CPC分类号： G11C11/4085 , G11C8/12 , G11C11/401 , G11C11/4087 , G11C29/50
摘要： A dynamic random access memory includes a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.
摘要翻译：动态随机存取存储器包括以行和列排列的多个动态存储单元，连接到同一行上的存储单元的字线，连接到同一列上的存储单元的位线，字线选择电路，响应于内部地址信号，字线驱动电压源，字线驱动电路选择任意一行的字线选择功能，具有连接在字线驱动电压源和字线，用于响应于字线选择电路的输出信号驱动字线;以及控制电路，用于响应于从外部输入的电压应力测试控制信号，控制字线驱动电路，使得字线路驱动电路在接收到外部地址信号时，比在正常操作模式中选择的字线更多地驱动字线。

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