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31. 发明授权

US6140237A Damascene process for forming coplanar top surface of copper connector isolated by barrier layers in an insulating layer 有权
标题翻译：用于形成由绝缘层中的阻挡层隔离的铜连接器的共面顶表面的镶嵌工艺
公开(公告)号：US6140237A
公开(公告)日：2000-10-31
申请号：US294048
申请日：1999-04-19
申请人： Lap Chan , Jia Zhen Zheng
发明人： Lap Chan , Jia Zhen Zheng
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76843 , H01L23/53238 , H01L2924/0002
摘要： A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.
摘要翻译：描述了在集成电路中制造铜互连的结构和方法。该结构是镶嵌铜连接器，其上表面与嵌入其中的绝缘层的上表面共面。通过两个阻挡层防止铜从连接器的扩散。一个位于连接器和绝缘层之间的界面处，而第二屏障是覆盖连接器的上表面的绝缘层。镶嵌工艺包括用铜填充绝缘体表面的沟槽，然后通过化学去除多余的沟槽。抛光。由于光致抗蚀剂从不与铜直接接触，因此已经有效地消除了抗蚀剂灰化期间铜氧化的问题。

32. 发明授权

US5948700A Method of planarization of an intermetal dielectric layer using chemical mechanical polishing 失效
标题翻译：使用化学机械抛光对金属间电介质层进行平面化的方法
公开(公告)号：US5948700A
公开(公告)日：1999-09-07
申请号：US650694
申请日：1996-05-20
申请人： Jia Zhen Zheng , Lap Chan
发明人： Jia Zhen Zheng , Lap Chan
IPC分类号： H01L21/3105 , H01L21/306
CPC分类号： H01L21/31053
摘要： A method of planarizing integrated circuit wafers using chemical mechanical polishing with an automatic end point and without using an etchback step. An electrode pattern is formed in a layer of soft metal, such as Al/Cu/Si, capped with a layer of hard metal such as tungsten. A layer of first oxide, a layer of spin on glass, and a layer of second oxide are formed over the electrode pattern. The layer of first oxide, the layer of spin on glass, and the layer of second oxide are then planarized using chemical mechanical polishing. The hard metal cap on the electrode pattern can not be removed by the chemical mechanical polishing and forms an automatic end point. The electric current powering the motor driving the chemical mechanical polishing changes when the hard metal cap is reached and this change can be used to detect the end point.
摘要翻译：使用具有自动终点的化学机械抛光并且不使用回蚀步骤来平面化集成电路晶片的方法。电极图案形成在诸如Al / Cu / Si的软金属层中，其被诸如钨的硬金属层覆盖。在电极图案之上形成第一氧化物层，玻璃上的自旋层和第二氧化物层。然后使用化学机械抛光使第一氧化物层，玻璃上的自旋层和第二氧化物层平坦化。电极图案上的硬金属盖不能通过化学机械抛光去除并形成自动终点。驱动化学机械抛光的电机的电流在达到硬金属帽时发生变化，并且可以使用该变化来检测终点。

33. 发明授权

US5900672A Barrier layer 失效
标题翻译：铜互连与顶部阻挡层
公开(公告)号：US5900672A
公开(公告)日：1999-05-04
申请号：US876915
申请日：1997-06-16
申请人： Lap Chan , Jia Zhen Zheng
发明人： Lap Chan , Jia Zhen Zheng
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76834 , H01L21/76843 , H01L23/53238 , H01L2924/0002
摘要： A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.
摘要翻译：描述了在集成电路中制造铜互连的结构和方法。该结构是镶嵌铜连接器，其上表面与嵌入其中的绝缘层的上表面共面。通过两个阻挡层防止铜从连接器的扩散。一个位于连接器和绝缘层之间的界面处，而第二屏障是覆盖连接器的上表面的绝缘层。镶嵌工艺包括用铜填充绝缘体表面的沟槽，然后通过化学去除多余的沟槽。抛光。由于光致抗蚀剂从不与铜直接接触，因此已经有效地消除了抗蚀剂灰化期间铜氧化的问题。

34. 发明授权

US5744376A Method of manufacturing copper interconnect with top barrier layer 失效
标题翻译：制造具有顶部阻挡层的铜互连的方法
公开(公告)号：US5744376A
公开(公告)日：1998-04-28
申请号：US630709
申请日：1996-04-08
申请人： Lap Chan , Jia Zhen Zheng
发明人： Lap Chan , Jia Zhen Zheng
IPC分类号： H01L21/768 , H01L23/532 , H01L21/28
CPC分类号： H01L21/76834 , H01L21/76843 , H01L23/53238 , H01L2924/0002
摘要： A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer ,while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.
摘要翻译：描述了在集成电路中制造铜互连的结构和方法。该结构是镶嵌铜连接器，其上表面与嵌入其中的绝缘层的上表面共面。通过两个阻挡层防止铜从连接器的扩散。一个位于连接器和绝缘层之间的界面处，而第二屏障是覆盖连接器的上表面的绝缘层。镶嵌工艺包括用铜填充绝缘体表面的沟槽，然后通过化学去除多余的沟槽。抛光。由于光致抗蚀剂从不与铜直接接触，因此已经有效地消除了抗蚀剂灰化期间铜氧化的问题。

35. 发明授权

US07049201B2 Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy 有权
标题翻译：使用自对准外延的异质结双极晶体管的方法和装置
公开(公告)号：US07049201B2
公开(公告)日：2006-05-23
申请号：US10703297
申请日：2003-11-06
申请人： Purakh Raj Verma , Shao-Fu Sanford Chu , Lap Chan , Jian Xun Li , Jia Zhen Zheng
发明人： Purakh Raj Verma , Shao-Fu Sanford Chu , Lap Chan , Jian Xun Li , Jia Zhen Zheng
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the collector region, a base structure of a compound semiconductive material in the base cavity, a window in the insulating layer over the base cavity, an emitter structure in the window, an interlevel dielectric layer, and connections through the interlevel dielectric layer to the base structure, the emitter structure, and the collector region. The base structure and the emitter structure preferably are formed in the same processing chamber.
摘要翻译：一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，半导体衬底上的多个绝缘层的半导体衬底，在集电极区域上具有基腔的多个绝缘层中的至少一个，基腔中的复合半导体材料的基底结构，在基底腔上的绝缘层中的窗口，窗口中的发射极结构，层间介电层以及通过层间介电层到基底结构的连接，发射极结构和收集器区域。基底结构和发射极结构优选地形成在相同的处理室中。

36. 发明授权

US06924202B2 Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact 有权
标题翻译：具有自对准发射极和侧壁基极接触的异质结双极晶体管
公开(公告)号：US06924202B2
公开(公告)日：2005-08-02
申请号：US10683142
申请日：2003-10-09
申请人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
发明人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
IPC分类号： H01L21/331 , H01L29/08 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/0817 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer and the collector region. An intrinsic base structure having a sidewall portion and a bottom portion is formed in the base trench. An insulating spacer is formed over the sidewall portion of the intrinsic base structure, and an emitter structure is formed over the insulating spacer and the bottom portion of the intrinsic base structure. An interlevel dielectric layer is formed over the base contact layer and the emitter structure. Connections are formed through the interlevel dielectric layer to the collector region, the base contact layer, and the emitter structure. The intrinsic base structure is silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：提供了具有集电极区域的半导体衬底的异质结双极晶体管（HBT）及其制造方法。基极接触层形成在集电极区域上，基底沟槽形成在基极接触层和集电极区域中。在基底沟槽中形成具有侧壁部分和底部的本征基底结构。在本征基底结构的侧壁部分上形成绝缘间隔物，并且在绝缘间隔物和本征基底结构的底部上形成发射极结构。在基极接触层和发射极结构之上形成层间电介质层。通过层间绝缘层到集电极区，基极接触层和发射极结构形成连接。本征基础结构是硅和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

37. 发明授权

US06908824B2 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US06908824B2
公开(公告)日：2005-06-21
申请号：US10703284
申请日：2003-11-06
申请人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
发明人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/737
摘要： A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：提供一种用于制造横向异质结双极晶体管（HBT）的方法，包括半导体衬底上的第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

38. 发明授权

US06881976B1 Heterojunction BiCMOS semiconductor 失效
标题翻译：异质结BiCMOS半导体
公开(公告)号：US06881976B1
公开(公告)日：2005-04-19
申请号：US10705163
申请日：2003-11-06
申请人： Jia Zhen Zheng , Lap Chan , Shao-fu Sanford Chu
发明人： Jia Zhen Zheng , Lap Chan , Shao-fu Sanford Chu
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/108 , H01L29/04 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L29/66242 , H01L21/8249 , H01L27/0623
摘要： A BiCMOS semiconductor, and manufacturing method therefore, is provided. A semiconductor substrate having a collector region is provided. A pseudo-gate is formed over the collector region. An emitter window is formed in the pseudo-gate to form an extrinsic base structure. An undercut region beneath a portion of the pseudo-gate is formed to provide an intrinsic base structure in the undercut region. An emitter structure is formed in the emitter window over the intrinsic base structure. An interlevel dielectric layer is formed over the semiconductor substrate, and connections are formed through the interlevel dielectric layer to the collector region, the extrinsic base structure, and the emitter structure. The intrinsic base structure comprises a compound semiconductive material such as silicon and silicon-germanium, or silicon-germanium-carbon, or combinations thereof.
摘要翻译：因此，提供BiCMOS半导体及其制造方法。提供具有集电极区域的半导体衬底。在集电极区域上形成伪栅极。在伪栅极中形成发射器窗口以形成外部基极结构。在伪栅极的一部分下面的底切区域形成为在底切区域中提供内部基极结构。发射极结构在内部基极结构的发射极窗口中形成。在半导体衬底上形成层间电介质层，并且通过层间电介质层到集电极区域，非本征基极结构和发射极结构形成连接。本征基础结构包括诸如硅和硅 - 锗的复合半导体材料或硅 - 锗 - 碳或其组合。

39. 发明授权

US07382027B2 MOSFET device with low gate contact resistance 有权
标题翻译：具有低栅极接触电阻的MOSFET器件
公开(公告)号：US07382027B2
公开(公告)日：2008-06-03
申请号：US11045958
申请日：2005-01-28
申请人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
发明人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76802 , H01L21/76829
摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.
摘要翻译：描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作下的噪声性能，增加的单位功率增益频率（f max）和减小的栅极延迟。

40. 发明授权

US06972237B2 Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth 有权
公开(公告)号：US06972237B2
公开(公告)日：2005-12-06
申请号：US10725670
申请日：2003-12-01
申请人： Purakh Raj Verma , Shao-fu Sanford Chu , Lap Chan , Jia Zhen Zheng , Jian Xun Li
发明人： Purakh Raj Verma , Shao-fu Sanford Chu , Lap Chan , Jia Zhen Zheng , Jian Xun Li
IPC分类号： H01L21/331 , H01L29/737 , H01L21/8222
CPC分类号： H01L29/66242 , H01L29/737
摘要： A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent the intrinsic collector structure and under the extrinsic base structure. An emitter structure is formed adjacent the intrinsic base structure. An extrinsic collector structure is formed adjacent the intrinsic collector structure. A plurality of contacts is formed through an interlevel dielectric layer to the extrinsic collector structure, the extrinsic base structure, and the emitter structure.

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