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31. 发明授权

US06036744A Method and apparatus for making metallic iron 失效
公开(公告)号：US06036744A
公开(公告)日：2000-03-14
申请号：US818954
申请日：1997-03-14
申请人： Takuya Negami , Kazuo Kunii , Shinichi Inaba , Masataka Shimizu , Isao Kobayashi , Yoshimichi Takenaka , Toshihide Matsumura , Akira Uragami , Takashi Kujirai , Osamu Tsuchiya , Kimio Sugiyama , Shuzo Ito , Shoichi Kikuchi
发明人： Takuya Negami , Kazuo Kunii , Shinichi Inaba , Masataka Shimizu , Isao Kobayashi , Yoshimichi Takenaka , Toshihide Matsumura , Akira Uragami , Takashi Kujirai , Osamu Tsuchiya , Kimio Sugiyama , Shuzo Ito , Shoichi Kikuchi
IPC分类号： C21B13/00 , C21B13/10 , C21B15/00 , C21B11/06 , C22B1/20
CPC分类号： C21B13/0046 , C21B13/105 , Y02P10/136 , Y10T428/2991
摘要： A method of making metallic iron in which a compact, containing iron oxide such as iron ore or the like and a carbonaceous reductant such as coal or the like, is used as material, and the iron oxide is reduced through the application of heat, thereby making metallic iron. In the course of this reduction, a shell composed of metallic iron is generated and grown on the surface of the compact, and slag aggregates inside the shell. This reduction continues until substantially no iron oxide is present within the metallic iron shell. Subsequently, heating is further performed to melt the metallic iron and slag. Molten metallic iron and molten slag are separated one from the other, thereby obtaining metallic iron with a relatively high metallization ratio. Through the employment of an apparatus for making metallic iron of the present invention, the above-described method is efficiently carried out, and metallic iron having a high iron purity can be made continuously as well as productively not only from iron oxide having a high iron content but also from iron oxide having a relatively low iron content.

32. 发明授权

US5557274A Ad converter and magnetic recording/regenerating apparatus using the same 失效
标题翻译： Ad转换器和使用其的磁记录/再生装置
公开(公告)号：US5557274A
公开(公告)日：1996-09-17
申请号：US253551
申请日：1994-06-03
申请人： Tsuguyoshi Hirooka , Shoichi Miyazawa , Ryutaro Horita , Terumi Takashi , Akira Uragami
发明人： Tsuguyoshi Hirooka , Shoichi Miyazawa , Ryutaro Horita , Terumi Takashi , Akira Uragami
IPC分类号： G11B5/012 , G11B5/035 , G11B5/09 , G11B19/02 , G11B20/10 , G11B20/12 , H03M1/00 , H03M1/36 , H03M1/14
CPC分类号： H03M1/002 , G11B19/02 , G11B20/10 , G11B20/10009 , G11B5/012 , G11B20/1258 , G11B5/035 , G11B5/09 , H03M1/365
摘要： The present invention provides an AD converter which operates at high speed with low power consumption and a magnetic recording/regenerating apparatus using the same. The magnetic recording/regenerating apparatus has a current controller for switching the operating current of the comparator of the AD converter and an ADC controller for receiving an instruction of the conversion speed corresponding to the regenerating frequency. When the current controller receives an instruction for decreasing the conversion speed, it puts an operation state of the AD converter into a low power consumption state.
摘要翻译：本发明提供一种以低功耗高速运行的AD转换器和使用该AD转换器的磁记录/再生装置。磁记录/再生装置具有用于切换AD转换器的比较器的工作电流的电流控制器和用于接收与再生频率对应的转换速度的指令的ADC控制器。当电流控制器接收到用于降低转换速度的指令时，其将AD转换器的操作状态置于低功耗状态。

33. 发明授权

US5377136A Semiconductor integrated circuit device with built-in memory circuit group 失效
标题翻译：具有内置存储电路组的半导体集成电路器件
公开(公告)号：US5377136A
公开(公告)日：1994-12-27
申请号：US076874
申请日：1993-06-15
申请人： Yoji Nishio , Fumio Murabayashi , Shoichi Kotoku , Akira Uragami , Manabu Shibata , Yoshitatsu Kojima , Fumiaki Matsuzaki
发明人： Yoji Nishio , Fumio Murabayashi , Shoichi Kotoku , Akira Uragami , Manabu Shibata , Yoshitatsu Kojima , Fumiaki Matsuzaki
IPC分类号： G11C5/06 , G11C8/16
CPC分类号： G11C8/16 , G11C5/063
摘要： A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.
摘要翻译：公开了一种具有内置存储器电路组的半导体集成电路器件，其中从存储器电路组的数据交换部分附近的数据终端位置开始布线以减少布线的长度。因此，可以通过减少布线电容来提高操作速度，并且可以通过降低布线通道的占有率来减少退绕布线的比率。

34. 发明授权

US4645951A Semiconductor integrated circuit having a C-MOS internal logic block and an output buffer for providing ECL level signals 失效
标题翻译：具有C-MOS内部逻辑块的半导体集成电路和用于提供ECL电平信号的输出缓冲器
公开(公告)号：US4645951A
公开(公告)日：1987-02-24
申请号：US646110
申请日：1984-08-31
申请人： Akira Uragami
发明人： Akira Uragami
IPC分类号： H01L27/118 , H03K19/0175 , H03K19/018 , H03K19/0944 , H03K17/12 , H03K19/01
CPC分类号： H03K19/01812 , H01L24/06 , H01L24/49 , H03K19/017527 , H03K19/09448 , H01L2224/05554 , H01L2224/45144 , H01L2224/48247 , H01L2224/48257 , H01L24/45 , H01L24/48 , H01L27/11898 , H01L2924/00014 , H01L2924/13091 , H01L2924/14
摘要： A semiconductor integrated circuit is provided which combines an MOS internal logic circuit (C-MOS in the preferred embodiment) with input and output buffers which have pin-compatibility with ECL circuitry. An ECL-CMOS level-conversion input buffer circuit arranged for a C-MOS internal logic circuit has a pair of emitter-coupled transistors which are responsive to an input signal at an ECL level. Thus, the input buffer circuit operates at a high speed. A CMOS-ECL level-conversion output buffer circuit arranged for the C-MOS internal logic circuit has an amplifying transistor, which has its base responsive to the output signal of the C-MOS internal logic circuit, and an emitter-follower transistor which has its base responsive to the collector signal of said amplifying transistor for generating an output signal at an ECL level at its emitter. Thus, the output buffer circuit operates at a high speed. Utilizing such an arrangement, the circuit can obtain the benefits of lower power consumption for the C-MOS internal logic circuit together with high speed in the buffer stages and ECL compatibility.
摘要翻译：提供了一种半导体集成电路，其组合了MOS内部逻辑电路（在优选实施例中为C-MOS）与与ECL电路具有引脚兼容性的输入和输出缓冲器。布置用于C-MOS内部逻辑电路的ECL-CMOS电平转换输入缓冲电路具有一对响应于ECL电平的输入信号的发射极耦合晶体管。因此，输入缓冲电路以高速工作。为C-MOS内部逻辑电路配置的CMOS-ECL电平转换输出缓冲电路具有放大晶体管，其基极响应C-MOS内部逻辑电路的输出信号，并具有发射极跟随器晶体管，其具有其基极响应于所述放大晶体管的集电极信号，以在其发射极处产生ECL电平的输出信号。因此，输出缓冲电路以高速工作。利用这种布置，电路可以获得C-MOS内部逻辑电路的低功耗以及缓冲器级的高速和ECL兼容性的优点。

35. 发明申请

US20090217784A1 ORE REDUCTION PROCESS AND TITANIUM OXIDE AND IRON METALLIZATION PRODUCT 有权
标题翻译： ORE还原工艺和氧化钛和铁金属化产品
公开(公告)号：US20090217784A1
公开(公告)日：2009-09-03
申请号：US12430261
申请日：2009-04-27
申请人： John James Barnes , Stephen Erwin Lyke , Dat Nguyen , Mitsutaka Hino , Akira Uragami , Isao Kobayashi , Thomas Peter Battle , Joseph M. Shekiro, JR.
发明人： John James Barnes , Stephen Erwin Lyke , Dat Nguyen , Mitsutaka Hino , Akira Uragami , Isao Kobayashi , Thomas Peter Battle , Joseph M. Shekiro, JR.
IPC分类号： C22B1/14
CPC分类号： C21B13/105 , C21B3/04 , C21B13/0046 , C21B13/006 , Y02W30/542 , Y10T428/12056
摘要： The disclosure is directed to a process for producing separable iron and titanium oxides from an ore containing titanium oxide and ferric oxide, comprising: (a) forming agglomerates comprising carbon-based materials and the ore, the quantity of carbon of the agglomerates being sufficient for, at an elevated temperature, reducing ferric oxide to ferrous oxide and forming a ferrous oxide-rich molten slag, (b) introducing the agglomerates onto a carbon bed of a moving hearth furnace; (c) heating the agglomerates in the moving hearth furnace to a temperature sufficient for reducing and melting the agglomerates to produce a ferrous oxide-rich molten slag; (d) metallizing the ferrous oxide of the molten slag by reaction of the ferrous oxide and the carbon of the carbon bed at a furnace temperature sufficient for maintaining the slag in a molten state; and (e) solidifying the slag after metallization of the ferrous oxide to form a matrix of titanium oxide-rich slag having a plurality of metallic iron granules distributed there through; and (f) separating the metallic iron granules from the slag, the slag comprising greater than 85% titanium dioxide based on the entire weight of the matrix after separation of the metallic iron. The disclosure is also directed to a metallization product of a ferrous oxide-rich molten slag.
摘要翻译：本发明涉及从含有氧化钛和氧化铁的矿石中制备可分离的铁和钛氧化物的方法，其包括：（a）形成包含碳基材料和矿石的附聚物，附聚物的碳量足以在升高的温度下，将氧化亚铁还原成氧化亚铁，形成富含氧化亚铁的熔渣，（b）将附聚物引入移动的炉底炉的碳床上; （c）将移动的炉底炉中的附聚物加热至足以减少和熔化附聚物以产生富含氧化亚铁的熔渣的温度; （d）在足以使炉渣处于熔融状态的炉温下，通过氧化亚氮和碳床的碳的反应使熔渣的氧化亚铁金属化; 和（e）在氧化亚铁金属化之后固化炉渣，以形成富含氧化钛的炉渣的基体，其具有分布在其上的多个金属铁颗粒; 和（f）从矿渣中分离金属铁颗粒，在分离金属铁之后，炉渣基于基体的整个重量，含有大于85％的二氧化钛。本公开还涉及富含氧化亚铁的熔渣的金属化产物。

36. 发明授权

US06266200B1 Magnetic disk storage apparatus 失效
标题翻译：磁盘存储装置
公开(公告)号：US06266200B1
公开(公告)日：2001-07-24
申请号：US09438510
申请日：1999-11-12
申请人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
发明人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
IPC分类号： G11B509
CPC分类号： H03L7/093 , G11B5/012 , G11B20/1403 , G11B2020/10916 , H03K3/2821 , H03L7/089 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/099 , H03L7/107 , H03L2207/06 , H04L7/033
摘要： A magnetic disk storage apparatus having a magnetic disk-type storage medium; a head for reading data recorded on the magnetic disk-type storage medium, a processor, a phase synchronizing circuit having a controllable response characteristic and for outputting a clock signal to handle the data read from the magnetic disk-type storage medium, and a memory for storing information to control the response characteristic of the phase synchronizing circuit previously set in accordance with an access position on the magnetic disk-type storage medium. The processor generates the access position on the magnetic disk-type storage medium and data for commanding the control of the response characteristic of the phase synchronizing circuit in accordance with the information stored in the memory, and commands the control of the response characteristic by the data for the command, at a time consistent with a time of a seek operation of the head for the access position on the magnetic disk-type storage medium or a time before the seek operation of the head. Further, the response characteristic is controlled by the command.
摘要翻译：一种具有磁盘式存储介质的磁盘存储装置; 用于读取记录在磁盘式存储介质上的数据的磁头，处理器，具有可控响应特性的相位同步电路，以及用于输出时钟信号以处理从磁盘式存储介质读取的数据的存储器用于存储用于控制根据磁盘式存储介质上的存取位置预先设定的相位同步电路的响应特性的信息。处理器根据存储在存储器中的信息产生磁盘式存储介质上的访问位置和用于指示相位同步电路的响应特性的控制的数据，并且通过数据命令对响应特性的控制在与磁盘式存储介质上的访问位置的头部的寻道操作的时间或头部的搜索操作之前的时间相一致的时间。此外，响应特性由命令控制。

37. 发明授权

US5673058A One-chip semiconductor integrated circuit device capable of outputting analog color signal or digital color signal 失效
标题翻译：能够输出模拟彩色信号或数字彩色信号的单芯片半导体集成电路器件
公开(公告)号：US5673058A
公开(公告)日：1997-09-30
申请号：US621753
申请日：1996-03-22
申请人： Akira Uragami , Shinichi Kojima
发明人： Akira Uragami , Shinichi Kojima
IPC分类号： G09G5/04 , G06F1/32 , G06F3/14 , G09G3/36 , G09G5/00 , G09G5/06 , G09G5/36
CPC分类号： G09G5/06 , G09G5/366 , G06F3/1431
摘要： A semiconductor device (CPLT) of the invention comprises a first terminal (R) to which analog data is to be supplied, a digital/analog converter (DAC1) with its output coupled to the first terminal, a second terminal (R'0) to which digital data is to be supplied, a digital output circuit (DOB) with its output coupled to the second terminal, and a preparation circuit (PLM, SEL) which is coupled to respective inputs of the digital/analog converter and the digital output circuit. The preparation circuit prepares digital data to be processed (RR) for any one of input of the digital/analog converter and input of the digital output circuit.
摘要翻译：本发明的半导体器件（CPLT）包括：要向其提供模拟数据的第一端子（R），其输出耦合到第一端子的数模转换器（DAC1），第二端子（R'0）要向其提供数字数据的数字输出电路（DOB），其输出耦合到第二端子;以及准备电路（PLM，SEL），其耦合到数字/模拟转换器的相应输入端和数字输出端电路。准备电路为数字/模拟转换器的输入和数字输出电路的输入中的任何一个准备要处理的数字数据（RR）。

38. 发明授权

US5463504A Magnetic disk system and waveform equalizer therefor 失效
标题翻译：磁盘系统及其波形均衡器
公开(公告)号：US5463504A
公开(公告)日：1995-10-31
申请号：US62770
申请日：1993-05-18
申请人： Hiroshi Kimura , Shoichi Miyazawa , Ryutaro Horita , Kenichi Hase , Akihiko Hirano , Akira Uragami
发明人： Hiroshi Kimura , Shoichi Miyazawa , Ryutaro Horita , Kenichi Hase , Akihiko Hirano , Akira Uragami
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14
CPC分类号： G11B20/10046 , G11B20/10009 , G11B20/10222 , G11B20/1403 , G11B5/012 , G11B5/09 , G11B20/1258
摘要： A magnetic disk system which records and reproduces data on a magnetic disk at different data transfer rates depending on a track position on the disk includes a transversal waveform equalizing circuit which implements an optimal waveform shaping for a readout waveform. The waveform equalizing circuit consists of a register, a frequency synthesizer, a PLL, and a transversal circuit. The transversal circuit consists of variable delay circuits, variable gain amplifiers, and an adder. The frequency synthesizer produces a write clock signal having a frequency which corresponds to a value stored in the register which depends on the data transfer rate, and the PLL responds to the write clock signal to produce a control signal by which the delay time of the transversal circuit is controlled. Consequently, the delay characteristic is not affected by disparity of circuit components of the transversal circuit, and the write clock frequency and the delay time of the transversal circuit can be set to intended values by merely changing the value stored in the register in response to a variation of the data transfer rate.
摘要翻译：根据磁盘上的轨道位置以不同的数据传输速率记录和再现磁盘上的数据的磁盘系统包括对读出波形实现最佳波形整形的横向波形均衡电路。波形均衡电路由寄存器，频率合成器，PLL和横向电路组成。横向电路由可变延迟电路，可变增益放大器和加法器组成。频率合成器产生具有对应于存储在寄存器中的取决于数据传输速率的值的频率的写时钟信号，并且PLL响应于写时钟信号以产生控制信号，通过该控制信号，横向延迟时间电路被控制。因此，延迟特性不受横向电路的电路部件的不均匀影响，并且横向电路的写入时钟频率和延迟时间可以通过仅响应于一个变化来改变存储在寄存器中的值来设置为预期值数据传输速率的变化。

39. 发明授权

US5404250A Magnetic disk storage apparatus with phase sync circuit having controllable response characteristic 失效
标题翻译：具有可控响应特性的相位同步电路的磁盘存储装置
公开(公告)号：US5404250A
公开(公告)日：1995-04-04
申请号：US177694
申请日：1994-01-04
申请人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
发明人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
IPC分类号： G11B5/012 , G11B20/14 , H03K3/282 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/107 , H04L7/033 , G11B5/09 , H03K5/00 , H03L7/00
CPC分类号： H03L7/093 , G11B20/1403 , G11B5/012 , H03K3/2821 , H03L7/089 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/099 , H03L7/107 , G11B2020/10916 , H03L2207/06 , H04L7/033
摘要： A magnetic disk storage apparatus provides with a phase locked loop or a phase sync circuit including a phase comparator, a charge pump, a filter and a voltage-controlled oscillator. The phase sync circuit includes a register which is connected to an information processing system and adapted to store therein the response characteristics of the phase comparator, the charge pump, the filter and the voltage-controlled oscillator as instructed from the information processing system. In this way, in accordance with the information on the response characteristics from the information processing system, the phase sync circuit is controlled thereby to assure a stable operation even in the case of the data transfer speed varying between inner and outer track such as occurs in a magnetic disk.
摘要翻译：磁盘存储装置提供锁相环或包括相位比较器，电荷泵，滤波器和压控振荡器的相位同步电路。相位同步电路包括连接到信息处理系统并适合于从信息处理系统指示的其中存储相位比较器，电荷泵，滤波器和压控振荡器的响应特性的寄存器。以这种方式，根据关于来自信息处理系统的响应特性的信息，控制相位同步电路，从而即使在内外轨道之间变化的数据传输速度的情况下也可以确保稳定的操作，例如发生在磁盘。

40. 发明授权

US5398047A Semiconductor integrated circuit device including high-speed operating circuit and low-speed operating circuit, and system using the same 失效
标题翻译：半导体集成电路器件包括高速运算电路和低速运算电路，以及使用该系统的系统
公开(公告)号：US5398047A
公开(公告)日：1995-03-14
申请号：US112982
申请日：1993-08-30
申请人： Takashi Nara , Yasuhiro Kanzawa , Akira Uragami , Masaou Takahashi
发明人： Takashi Nara , Yasuhiro Kanzawa , Akira Uragami , Masaou Takahashi
IPC分类号： H01L21/822 , G09G5/06 , G09G5/36 , G09G5/39 , G11C5/14 , G11C7/00 , G11C7/06 , G11C8/10 , G11C8/16 , G11C11/401 , H01L21/82 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L27/118 , G09G5/18
CPC分类号： H01L27/11896 , G09G5/06 , G11C5/147 , G11C7/00 , G11C7/062 , G11C8/10 , G11C8/16 , G09G5/36 , G09G5/363
摘要： The semiconductor integrated circuit device formed on one semiconductor substrate employs a plurality of first and second circuit blocks constituting functions of the same kind. The first and second circuit blocks, however, are implemented with respectively different types of circuits. The type of circuit employed in the respective first and second circuit blocks is necessarily consistent with the particular operation speed requirements thereof, such as, in connection with high-speed and low-speed circuit requirements for writing into the memory of a display system.
摘要翻译：形成在一个半导体衬底上的半导体集成电路器件采用构成相同功能的多个第一和第二电路块。然而，第一和第二电路块分别由不同类型的电路实现。在相应的第一和第二电路块中使用的电路的类型必须与其特定的操作速度要求一致，例如结合用于写入显示系统的存储器的高速和低速电路要求。

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