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31. 发明申请

US20060088247A1 ONE-PIECE FIBER OPTIC RECEPTACLE HAVING CHAMFER AND ALIGNMENT RIBS 有权
标题翻译：具有切割和对准RIBS的单纤维光学接收器
公开(公告)号：US20060088247A1
公开(公告)日：2006-04-27
申请号：US10971884
申请日：2004-10-22
申请人： Hieu Tran , Xin Liu , James Luther , Thomas Theuerkorn , Charles Yow
发明人： Hieu Tran , Xin Liu , James Luther , Thomas Theuerkorn , Charles Yow
IPC分类号： G02B6/38
CPC分类号： G02B6/3874
摘要： A one-piece fiber optic receptacle is provided for aligning and optically connecting a plug ferrule with a back-side ferrule of like configuration. The fiber optic receptacle includes a receptacle housing defining an internal cavity opening through an external end and an opposed internal end, an alignment sleeve disposed within the internal cavity and received within the internal end of the receptacle housing, and a sleeve retainer secured to the internal end of the receptacle housing and operable for providing access to the alignment sleeve from the internal end of the receptacle housing. The alignment sleeve includes a chamfer for guiding the back-side ferrule into the alignment sleeve. The sleeve retainer has an opening and a plurality of alignment ribs disposed about the opening for permitting angular rotation of the alignment sleeve relative to the sleeve retainer during insertion of the plug ferrule and the back-side ferrule into the alignment sleeve.
摘要翻译：提供一体式光纤插座，用于对准和光学连接插头套圈与类似结构的背面套圈。光纤插座包括容纳壳体，其限定通过外部端部和相对的内部端部的内部空腔开口，配置套筒，其设置在内部空腔内并容纳在插座壳体的内部端部内，并且套筒保持器固定到内部插座壳体的端部并且可操作以从插座壳体的内端提供对准套筒的接近。对准套筒包括用于将后侧套圈引导到对准套筒中的倒角。套筒保持器具有一个开口和多个排列的肋条，围绕该开口设置，用于允许对准套筒相对于套筒保持器的角度旋转，以将插头套圈和后侧套圈插入对准套筒中。

32. 发明申请

US20050249006A1 Low voltage high speed sensing 有权
标题翻译：低电压高速感应
公开(公告)号：US20050249006A1
公开(公告)日：2005-11-10
申请号：US10838999
申请日：2004-05-04
申请人： Hieu Tran , Sang Nguyen , Hung Nguyen
发明人： Hieu Tran , Sang Nguyen , Hung Nguyen
IPC分类号： G11C7/00 , G11C7/06 , G11C11/56
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

33. 发明申请

US20050104116A1 Stacked gate memory cell with erase to gate, array, and method of manufacturing 有权
标题翻译：具有擦除到栅极，阵列和制造方法的堆叠栅极存储单元
公开(公告)号：US20050104116A1
公开(公告)日：2005-05-19
申请号：US10714243
申请日：2003-11-13
申请人： Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
发明人： Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115 , H01L29/7885
摘要： A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.
摘要翻译：堆叠式非易失性存储器浮栅器件具有控制栅极。通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。最后，为了增加密度，可以在沟槽中制造每个单元。

34. 发明申请

US20080080817A1 Fiber optic drop cables and preconnectorized assemblies having toning portions 有权
标题翻译：光纤分支电缆和具有调色部分的预连接组件
公开(公告)号：US20080080817A1
公开(公告)日：2008-04-03
申请号：US11980938
申请日：2007-10-31
申请人： Stuart Melton , David Thompson , Michael Gimblet , Hieu Tran , Richard Wagman , Xin Liu
发明人： Stuart Melton , David Thompson , Michael Gimblet , Hieu Tran , Richard Wagman , Xin Liu
IPC分类号： G02B6/36
CPC分类号： G02B6/3849 , G02B6/3816 , G02B6/3873 , G02B6/3879 , G02B6/3887 , G02B6/3893 , G02B6/4429 , G02B6/4433 , G02B6/4471
摘要： A preconnectorized outdoor cable streamlines the deployment of optical waveguides into the last mile of an optical network. The preconnectorized outdoor cable includes a cable and at least one plug connector. The plug connector is attached to a first end of the cable, thereby connectorizing at least one optical waveguide. The cable has at least one optical waveguide, at least one tensile element, and a cable jacket. Various cable designs such as figure-eight or flat cables may be used with the plug connector. In preferred embodiments, the plug connector includes a crimp assembly having a crimp housing and a crimp band. The crimp housing has two half-shells being held together by the crimp band for securing the at least one tensile element. When fully assembled, the crimp housing fits into a shroud of the preconnectorized cable. The shroud aides in mating the preconnectorized cable with a complimentary receptacle.
摘要翻译：预先连接的室外电缆可以将光波导的部署简化到光网络的最后一英里。预连接器室外电缆包括电缆和至少一个插头连接器。插头连接器附接到电缆的第一端，从而将至少一个光波导连接起来。电缆具有至少一个光波导，至少一个拉伸元件和电缆护套。诸如图八或扁平电缆的各种电缆设计可以与插头连接器一起使用。在优选实施例中，插头连接器包括具有压接壳体和压接带的压接组件。卷边壳体具有两个半壳，通过卷边带固定在一起，用于固定至少一个拉伸元件。当完全组装时，压接壳体装配到预连接电缆的护罩中。护罩可以将预连接电缆与互补的插座相配合。

35. 发明申请

US20070165436A1 High-speed and low-power differential non-volatile content addressable memory cell and array 有权
公开(公告)号：US20070165436A1
公开(公告)日：2007-07-19
申请号：US11717922
申请日：2007-03-13
申请人： Vishal Sarin , Hieu Tran , Isao Nojima
发明人： Vishal Sarin , Hieu Tran , Isao Nojima
IPC分类号： G11C7/00 , G11C15/00 , G11C5/14 , G11C7/06
CPC分类号： G11C14/00 , G11C15/046
摘要： A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements.

36. 发明申请

US20070147131A1 Flash memory array system including a top gate memory cell 有权
公开(公告)号：US20070147131A1
公开(公告)日：2007-06-28
申请号：US11707341
申请日：2007-02-16
申请人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
发明人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

37. 发明申请

US20070147111A1 Flash memory array system including a top gate memory cell 有权
标题翻译：包括顶栅存储单元的闪存阵列系统
公开(公告)号：US20070147111A1
公开(公告)日：2007-06-28
申请号：US11707343
申请日：2007-02-16
申请人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
发明人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

38. 发明申请

US20070081389A1 Method and apparatus for systematic and random variation and mismatch compensation for multilevel flash memory operation 有权
标题翻译：用于多级闪存操作的系统和随机变化和失配补偿的方法和装置
公开(公告)号：US20070081389A1
公开(公告)日：2007-04-12
申请号：US11235894
申请日：2005-09-26
申请人： Hieu Tran , Hung Nguyen
发明人： Hieu Tran , Hung Nguyen
IPC分类号： G11C16/06 , G11C11/34
CPC分类号： G11C16/28 , G11C7/02 , G11C7/062 , G11C7/08 , G11C11/5642 , G11C16/30
摘要： Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a triple well is used with the variable bulk voltage. Differential sense amplifiers with various offset compensation are included. Intentional offset creation for useful purpose is also included.
摘要翻译：公开了用于存储器感测系统的随机或系统失配补偿的方法和装置。感测放大器包括用于将感测晶体管的体积设置为不同于驱动感测晶体管的电压的电压的体电压源。对于NMOS感测晶体管，使用三重阱作为可变体电压。包括各种偏移补偿的差分放大器。有意义的意图偏移创建也包括在内。

39. 发明申请

US20070077010A1 Fiber optic drop cables and preconnectorized assemblies having toning portions 有权
标题翻译：光纤分支电缆和具有调色部分的预连接组件
公开(公告)号：US20070077010A1
公开(公告)日：2007-04-05
申请号：US11526315
申请日：2006-09-25
申请人： Stuart Melton , David Thompson , Michael Gimblet , Hieu Tran , Richard Wagman , Xin Liu
发明人： Stuart Melton , David Thompson , Michael Gimblet , Hieu Tran , Richard Wagman , Xin Liu
IPC分类号： G02B6/38 , G02B6/36
CPC分类号： G02B6/447 , G02B6/3816 , G02B6/3821 , G02B6/3849 , G02B6/3869 , G02B6/387 , G02B6/3873 , G02B6/3879 , G02B6/3885 , G02B6/3887 , G02B6/3894 , G02B6/3897 , G02B6/4405 , G02B6/4429 , G02B6/4433 , G02B6/4471
摘要： A preconnectorized outdoor cable streamlines the deployment of optical waveguides into the last mile of an optical network. The preconnectorized outdoor cable includes a cable and at least one plug connector. The plug connector is attached to a first end of the cable, thereby connectorizing at least one optical waveguide. The cable has at least one optical waveguide, at least one tensile element, and a cable jacket. Various cable designs such as figure-eight or flat cables may be used with the plug connector. In preferred embodiments, the plug connector includes a crimp assembly having a crimp housing and a crimp band. The crimp housing has two half-shells being held together by the crimp band for securing the at least one tensile element. When fully assembled, the crimp housing fits into a shroud of the preconnectorized cable. The shroud aides in mating the preconnectorized cable with a complimentary receptacle.
摘要翻译：预先连接的室外电缆可以将光波导的部署简化到光网络的最后一英里。预连接器室外电缆包括电缆和至少一个插头连接器。插头连接器附接到电缆的第一端，从而将至少一个光波导连接起来。电缆具有至少一个光波导，至少一个拉伸元件和电缆护套。诸如图八或扁平电缆的各种电缆设计可以与插头连接器一起使用。在优选实施例中，插头连接器包括具有压接壳体和压接带的压接组件。卷边壳体具有两个半壳，通过卷边带固定在一起，用于固定至少一个拉伸元件。当完全组装时，压接壳体装配到预连接电缆的护罩中。护罩可以将预连接电缆与互补的插座相配合。

40. 发明申请

US20070076489A1 Word line voltage boosting circuit and a memory array incorporating same 有权
公开(公告)号：US20070076489A1
公开(公告)日：2007-04-05
申请号：US11241582
申请日：2005-09-30
申请人： Ya-Fen Lin , Elbert Lin , Hieu Tran , Jack Frayer , Bomy Chen
发明人： Ya-Fen Lin , Elbert Lin , Hieu Tran , Jack Frayer , Bomy Chen
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C16/08
摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

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