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31. 发明授权

US07072781B1 Architecture for generating adaptive arbitrary waveforms 失效
标题翻译：用于生成自适应任意波形的体系结构
公开(公告)号：US07072781B1
公开(公告)日：2006-07-04
申请号：US10885284
申请日：2004-07-06
申请人： Eugen Gershon , David Gaun , Colin S. Bill , Tzu-Ning Fang
发明人： Eugen Gershon , David Gaun , Colin S. Bill , Tzu-Ning Fang
IPC分类号： G01R31/36
CPC分类号： G01R31/31924 , G01R31/3167 , G01R31/31908 , G11C29/56 , G11C29/56004
摘要： A test system having a feedback loop that facilitates adjusting an output test waveform to a DUT/CUT (Device Under Test/Circuit Under Test) on-the-fly according to changing DUT/CUT parameters. The system includes a tester having an arbitrary waveform generator (AWG) and a data acquisition system (DAS) that monitors the status of the DUT/CUT. The AWG and DAS connect to the DUT/CUT through a feedback loop where the AWG outputs the test waveform to the DUT/CUT, the DAS monitors the DUT/CUT parameters, and the DAS analyzes and communicates changes to the AWG to effect changes in the output waveform, when desired. The AWG builds the output waveform in small slices (or segments) that are assembled together through a process of selection and calibration. The feedback architecture facilitates a number of changes in the output waveform, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform.
摘要翻译：具有反馈回路的测试系统，其根据改变的DUT / CUT参数，有助于将DUT / CUT（被测设备/待测电路）的输出测试波形实时调整。该系统包括具有任意波形发生器（AWG）的测试器和监视DUT / CUT的状态的数据采集系统（DAS）。 AWG和DAS通过反馈回路连接到DUT / CUT，AWG将测试波形输出到DUT / CUT，DAS监视DUT / CUT参数，DAS分析并传送AWG的变化，以实现更改输出波形。 AWG通过选择和校准过程组装在一起的小片（或片段）中构建输出波形。反馈架构有助于输出波形的一些变化，包括预先组装的切片的原始顺序的改变以及输出波形的幅度/形状的变化。

32. 发明授权

US06205059B1 Method for erasing flash electrically erasable programmable read-only memory (EEPROM) 有权
标题翻译：擦除闪存电可擦除可编程只读存储器（EEPROM）的方法
公开(公告)号：US06205059B1
公开(公告)日：2001-03-20
申请号：US09166384
申请日：1998-10-05
申请人： Ravi P. Gutala , Jonathan S. Su , Colin S. Bill
发明人： Ravi P. Gutala , Jonathan S. Su , Colin S. Bill
IPC分类号： G11C1604
CPC分类号： G11C16/16
摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells, a power supply, and a controller which cooperates with the power supply to apply an erase pulse to the cells, and then erase verify a first byte of cells in each sector. If the first bytes in any sector has not passed erase verify, another erase pulse is applied to the cells of those sectors, and the first byte in each sector which did not pass erase verify the first time is erase verified again. This procedure is continued until the first byte in each sector has passed erase verify. Then, the sectors are processed in sequence to erase and erase verify every cell. First, an erase pulse is applied to all of the cells in the sector. Then, the first byte is erase verified. If the first byte passes erase verify (which it will because it did previously), the next byte is erase verified. Whenever a particular byte does not pass erase verify, another erase pulse is applied to all of the cells in the sector, and the particular cell is again erase verified. This procedure is sequentially performed on all of the bytes in the sector, or alternatively on the cells individually, until all of the cells have passed erase verify.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）包括多个场效应晶体管存储器单元，电源和与电源配合以向单元施加擦除脉冲的控制器，然后擦除验证每个扇区中单元格的第一个字节。如果任何扇区中的第一个字节没有通过擦除验证，则另一个擦除脉冲被施加到这些扇区的单元，而不通过擦除的每个扇区中的第一个字节在第一次再次被擦除验证。该过程继续，直到每个扇区中的第一个字节已经通过擦除验证。然后，扇区按顺序进行处理，以擦除和擦除每个单元的验证。首先，擦除脉冲被施加到扇区中的所有单元。然后，第一个字节被擦除验证。如果第一个字节通过擦除验证（由于之前已经执行了该验证），则下一个字节被擦除验证。每当特定字节不通过擦除验证时，另一个擦除脉冲被施加到扇区中的所有单元，并且特定单元被再次擦除验证。该过程顺序地在扇区中的所有字节上或者单独地在单元上执行，直到所有单元已经通过擦除验证。

33. 发明授权

US6147906A Method and system for saving overhead program time in a memory device 有权
标题翻译：用于在存储器件中节省开销程序时间的方法和系统
公开(公告)号：US6147906A
公开(公告)日：2000-11-14
申请号：US419695
申请日：1999-10-14
申请人： Colin S. Bill , Shigekazu Yamada
发明人： Colin S. Bill , Shigekazu Yamada
IPC分类号： G11C16/22 , G11C16/30 , G11C16/04
CPC分类号： G11C16/30 , G11C16/225
摘要： The present invention discloses a method for saving overhead programming time in a flash memory. In the preferred embodiment of the invention, a wordline voltage generation circuit and a bitline voltage generation circuit are electrically connected with a comparator circuit. During the programming operation, the comparator circuit compares a wordline programming voltage and a bitline enabling voltage generated by the voltage generation circuits to determine when the programming voltages reach a predetermined voltage level. Once the predetermined voltage level is reached, the comparator circuit sends an output signal to a state machine that initiates programming for at least one cell. The present invention provides advantages over prior methods of programming by reducing the time period that the state machine waits to initiate programming.
摘要翻译：本发明公开了一种在闪速存储器中节省开销编程时间的方法。在本发明的优选实施例中，字线电压产生电路和位线电压产生电路与比较器电路电连接。在编程操作期间，比较器电路比较字线编程电压和由电压产生电路产生的位线使能电压，以确定编程电压何时达到预定电压电平。一旦达到预定的电压电平，比较器电路将一个输出信号发送到启动至少一个单元的编程的状态机。本发明通过减少状态机等待启动编程的时间段来提供优于现有编程方法的优点。

34. 发明授权

US5875130A Method for programming flash electrically erasable programmable read-only memory 失效
标题翻译：闪存电可擦除可编程只读存储器的编程方法
公开(公告)号：US5875130A
公开(公告)日：1999-02-23
申请号：US085705
申请日：1998-05-27
申请人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chan , Colin S. Bill
发明人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chan , Colin S. Bill
IPC分类号： G11C16/10 , G11C16/34 , G11C13/00
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/3404
摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a semiconductor substrate, and a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate formed on the substrate. A controller controls a power source to apply an operational pulse to the drain of a cell, and apply a source to substrate bias voltage to the cell while the operational pulse is being applied thereto, the bias voltage having a value selected to reduce or substantially eliminate leakage current in the cell. The operational pulse can be an overerase correction pulse. In this case, a voltage which is substantially equal to the bias voltage is applied to the control gate for the duration of the overerase correction pulse. The operational pulse can also be a programming pulse. In this case, a voltage which is higher than the bias voltage is applied to the control gate of the selected wordline for the duration of the programming pulse. The bias voltage is preferably applied during both the overerase correction and programming pulses, reducing the power requirements and reducing the background leakage of the cells to a level at which program, read and overerase correction operations can be operatively performed.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）包括半导体衬底和多个场效应晶体管存储单元，每个具有形成在衬底上的源极，漏极，浮置栅极和控制栅极。控制器控制电源以将操作脉冲施加到单元的漏极，并且在施加操作脉冲时将源施加到单元的衬底偏置电压，所述偏置电压具有被选择为减少或基本上消除的值电池中的漏电流。操作脉冲可以是过高修正脉冲。在这种情况下，在过扫描校正脉冲的持续时间内，向控制栅极施加基本上等于偏置电压的电压。操作脉冲也可以是编程脉冲。在这种情况下，在编程脉冲的持续时间内，将高于偏置电压的电压施加到所选字线的控制栅极。偏置电压优选地在过电压过程校正和编程脉冲期间都被施加，从而降低功率需求并将电池的背景泄漏减小到能够可操作地执行程序，读取和过电压校正操作的电平。

35. 发明授权

US08098521B2 Method of providing an erase activation energy of a memory device 有权
标题翻译：提供存储器件的擦除激活能的方法
公开(公告)号：US08098521B2
公开(公告)日：2012-01-17
申请号：US11095849
申请日：2005-03-31
申请人： Michael A. VanBuskirk , Colin S. Bill , Zhida Lan , Tzu-Ning Fang
发明人： Michael A. VanBuskirk , Colin S. Bill , Zhida Lan , Tzu-Ning Fang
IPC分类号： G11C11/34
CPC分类号： G11C13/0014 , B82Y10/00
摘要： A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active layer. The memory device may be programmed to have for the programmed memory device a first erase activation energy. The present method provides for the programmed memory device a second erase activation energy greater than the first erase activation energy.
摘要翻译：一次写入多次存储器件由第一和第二电极，第一和第二电极之间的无源层以及第一和第二电极之间的有源层组成。通过从被动层提供带电物质到活性层来对存储器件进行编程。存储器件可以被编程为使编程的存储器件具有第一擦除激活能量。本方法为编程的存储器件提供大于第一擦除激活能量的第二擦除激活能量。

36. 发明授权

US07791947B2 Non-volatile memory device and methods of using 有权
标题翻译：非易失性存储器件及其使用方法
公开(公告)号：US07791947B2
公开(公告)日：2010-09-07
申请号：US11972312
申请日：2008-01-10
申请人： Michael A. VanBuskirk , Colin S. Bill , Takao Akaogi
发明人： Michael A. VanBuskirk , Colin S. Bill , Takao Akaogi
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , H01L27/115
摘要： The present disclosure adjusts the voltage threshold values of select gates of NAND strings. The select gates of the NAND string can be read, erased, and programmed.
摘要翻译：本公开调整NAND串的选择栅极的电压阈值。可以读取，擦除和编程NAND串的选择栅极。

37. 发明申请

US20090180330A1 NON-VOLATILE MEMORY DEVICE AND METHODS OF USING 有权
标题翻译：非易失性存储器件及其使用方法
公开(公告)号：US20090180330A1
公开(公告)日：2009-07-16
申请号：US11972312
申请日：2008-01-10
申请人： Michael A. VanBuskirk , Colin S. Bill , Takao Akaogi
发明人： Michael A. VanBuskirk , Colin S. Bill , Takao Akaogi
IPC分类号： G11C16/06 , G11C11/34
CPC分类号： G11C16/0483 , H01L27/115
摘要： The present disclosure adjusts the voltage threshold values of select gates of NAND strings. The select gates of the NAND string can be read, erased, and programmed.
摘要翻译：本公开调整NAND串的选择栅极的电压阈值。可以读取，擦除和编程NAND串的选择栅极。

38. 发明授权

US07035141B1 Diode array architecture for addressing nanoscale resistive memory arrays 有权
标题翻译：用于寻址纳米尺度电阻式存储器阵列的二极管阵列架构
公开(公告)号：US07035141B1
公开(公告)日：2006-04-25
申请号：US10990706
申请日：2004-11-17
申请人： Nicholas H. Tripsas , Colin S. Bill , Michael A. VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Daisy Cai , Suzette Pangrle , Steven Avanzino
发明人： Nicholas H. Tripsas , Colin S. Bill , Michael A. VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Daisy Cai , Suzette Pangrle , Steven Avanzino
IPC分类号： G11C11/36 , G11C27/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0007 , G11C2213/56 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021
摘要： The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages.
摘要翻译：本存储器结构包括第一导体，第二导体，连接到第二导体的电阻性存储单元，连接到电阻存储单元和第一导体的第一二极管，并且从电阻存储单元向前取向所述第一导体和连接到所述电阻性存储器单元和所述第一导体的第二二极管与所述第一二极管并联，并且在从所述电阻存储器单元到所述第一导体的相反方向上定向。第一和第二二极管具有不同的阈值电压。

39. 发明授权

US06400638B1 Wordline driver for flash memory read mode 有权
标题翻译：用于闪存读取模式的字线驱动程序
公开(公告)号：US06400638B1
公开(公告)日：2002-06-04
申请号：US09680344
申请日：2000-10-05
申请人： Shigekazu Yamada , Takao Akaogi , Colin S. Bill
发明人： Shigekazu Yamada , Takao Akaogi , Colin S. Bill
IPC分类号： G11C800
CPC分类号： G11C16/08 , G11C8/08
摘要： The present invention discloses a wordline voltage regulation method and system that provides a predetermined voltage as a wordline voltage to a plurality of wordlines during read mode. A supply voltage (Vcc) is regulated and temperature compensated by a wordline driver circuit to provide the predetermined voltage that is lower in magnitude than the magnitude of the supply voltage (Vcc). The wordline driver circuit is activated by an activation circuit when the read operation is initiated. During the read operation, the wordline driver circuit maintains the predetermined voltage during variations in the supply voltage (Vcc) as well as variations in a process load supplied by the wordline driver circuit.
摘要翻译：本发明公开了一种在读取模式期间向多个字线提供预定电压作为字线电压的字线电压调节方法和系统。电源电压（Vcc）由字线驱动器电路调节和温度补偿，以提供比电源电压（Vcc）的幅度更低的预定电压。当启动读取操作时，字线驱动器电路由激活电路激活。在读取操作期间，字线驱动器电路在电源电压（Vcc）的变化期间维持预定电压以及由字线驱动器电路提供的工艺负载的变化。

40. 发明授权

US6157572A Method for erasing flash electrically erasable programmable read-only memory (EEPROM) 失效
标题翻译：擦除闪存电可擦除可编程只读存储器（EEPROM）的方法
公开(公告)号：US6157572A
公开(公告)日：2000-12-05
申请号：US85680
申请日：1998-05-27
申请人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chen , Colin S. Bill
发明人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chen , Colin S. Bill
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/3445 , G11C16/16
摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of floating gate transistor memory cells, a plurality of wordlines connected to the cells and a power supply for generating erase pulses. A controller controls the power supply to apply an erase pulse to all wordlines which are not deselected. Then, an erase verify procedure is applied to the cells in sequence. If all cells connected to a wordline pass the erase verify test, the wordline is deselected such that subsequent erase pulses will not be applied to the wordline and possibly cause the cells to become overerased. In one embodiment of the invention, erase verify is performed on all of the cells after an erase pulse is applied. The erase operation is completed when all cells pass erase verify. In another embodiment, erase verify is applied to each cell in sequence, with erase pulses being applied until each current cell passes erase verify. The wordlines can be deselected individually or in groups. The invention results in a tightening of the threshold voltage distribution of the cells.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）包括多个浮栅晶体管存储单元，连接到单元的多个字线和用于产生擦除脉冲的电源。控制器控制电源以将擦除脉冲施加到未被取消选择的所有字线。然后，按顺序对单元应用擦除验证程序。如果连接到字线的所有单元都通过擦除验证测试，则字线被取消选择，使得后续的擦除脉冲不会被施加到字线并且可能导致单元变得过高。在本发明的一个实施例中，在施加擦除脉冲之后对所有单元执行擦除验证。当所有单元通过擦除验证时，擦除操作完成。在另一实施例中，按顺序对每个单元施加擦除验证，其中施加擦除脉冲，直到每个当前单元通过擦除验证。字母可以单独或分组取消选择。本发明导致电池的阈值电压分布的紧缩。

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