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31. 发明授权

US08427229B2 Integrated circuits with bi-directional charge pumps 有权
标题翻译：具有双向电荷泵的集成电路
公开(公告)号：US08427229B2
公开(公告)日：2013-04-23
申请号：US13038519
申请日：2011-03-02
申请人： Yvonne Lin , Tien-Chun Yang
发明人： Yvonne Lin , Tien-Chun Yang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/02 , G11C5/145 , H02M3/07
摘要： Integrated circuits such as memory arrays are coupled to a bi-directional charge pump that includes an input circuit and output circuit, and one or more pump stages coupled between the input circuit and the output circuit of the bi-directional charge pump. The output circuit includes a diode having an input and output and a transistor connected to the output of the diode and a ground potential. The input of the diode is electrically connected to the pump stages in a configuration that allows the charge pump to apply a positive or negative voltage to the memory array or other load.
摘要翻译：诸如存储器阵列的集成电路耦合到双向电荷泵，其包括输入电路和输出电路，以及耦合在双向电荷泵的输入电路和输出电路之间的一个或多个泵级。输出电路包括具有输入和输出的二极管和连接到二极管的输出和地电位的晶体管。二极管的输入以允许电荷泵将正或负电压施加到存储器阵列或其它负载的配置电连接到泵级。

32. 发明申请

US20120182058A1 NEGATIVE CHARGE PUMP 有权
标题翻译：负电荷泵
公开(公告)号：US20120182058A1
公开(公告)日：2012-07-19
申请号：US13005643
申请日：2011-01-13
申请人： Tien-Chun Yang , Yvonne Lin , Ming-Chieh Huang
发明人： Tien-Chun Yang , Yvonne Lin , Ming-Chieh Huang
IPC分类号： H03K3/00 , G05F1/10
CPC分类号： H03K5/15013 , H02M3/07 , H02M2003/071
摘要： A charge pump includes a first node configured to receive a first voltage and a second node coupled to the first node through a first transistor. The second node is configured to output a voltage having a greater voltage magnitude than the first voltage. A first capacitor is coupled to a third node, and a fourth node is configured to receive a first clock signal. The third node is disposed between a drain of the first transistor and the fourth node. A leaky circuit device is coupled in parallel with the first capacitor for draining charges of a first polarity away from the second node.
摘要翻译：电荷泵包括被配置为通过第一晶体管接收耦合到第一节点的第一电压和第二节点的第一节点。第二节点被配置为输出具有比第一电压更大的电压幅度的电压。第一电容器耦合到第三节点，并且第四节点被配置为接收第一时钟信号。第三节点设置在第一晶体管的漏极和第四节点之间。泄漏电路装置与第一电容并联耦合，用于从第二节点排出第一极性的电荷。

33. 发明授权

US08183913B2 Integrated circuits including a charge pump circuit and operating methods thereof 有权
标题翻译：包括电荷泵电路的集成电路及其操作方法
公开(公告)号：US08183913B2
公开(公告)日：2012-05-22
申请号：US12706886
申请日：2010-02-17
申请人： Steven Swei , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
发明人： Steven Swei , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/10 , G05F3/02 , H03L7/0895 , H03L7/0896 , H03L7/0898
摘要： An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
摘要翻译：集成电路包括第一电流源。第二电流源经由导线与第一电流源电耦合。开关电路耦合在第一电流源和第二电流源之间。第一电路耦合在第一节点和第二节点之间。第一节点设置在第一电流源和开关电路之间。第二节点与第一电流源耦合。第一电路被配置为基本上均衡第一节点和第二节点上的电压。第二电路耦合在第三节点和第四节点之间。第三节点设置在第二电流源和开关电路之间。第四节点被布置成与第二电流源耦合。第二电路被配置为基本上均衡第三节点和第四节点上的电压。

34. 发明授权

US07961050B1 Integrated circuits including an equalizer and operating methods thereof 有权
标题翻译：集成电路，包括均衡器及其操作方法
公开(公告)号：US07961050B1
公开(公告)日：2011-06-14
申请号：US12706872
申请日：2010-02-17
申请人： Yuwen Swei , Tien-Chun Yang , Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang
发明人： Yuwen Swei , Tien-Chun Yang , Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang
IPC分类号： H03F3/04
CPC分类号： H03F3/45197 , H03F3/45183 , H03F3/45192 , H03F2203/45292 , H03F2203/45458 , H03F2203/45496 , H03F2203/45562 , H03F2203/45631 , H03F2203/45644 , H03F2203/45686 , H03F2203/45702
摘要： An integrated circuit includes a differential amplifier. The differential amplifier includes at least one output end. A circuit is coupled with the at least one output end of the differential amplifier. The circuit does not include a resistor-capacitor (RC) network and is configured for providing a negative impedance to the differential amplifier for adjusting a direct current (DC) gain of the integrated circuit.
摘要翻译：集成电路包括差分放大器。差分放大器包括至少一个输出端。电路与差分放大器的至少一个输出端耦合。该电路不包括电阻 - 电容（RC）网络，并被配置为向差分放大器提供负阻抗以调整集成电路的直流（DC）增益。

35. 发明授权

US07142454B2 System and method for Y-decoding in a flash memory device 有权
标题翻译：闪存设备中Y解码的系统和方法
公开(公告)号：US07142454B2
公开(公告)日：2006-11-28
申请号：US10243315
申请日：2002-09-12
申请人： Tien-Chun Yang , Ming-Huei Shieh , Kurihara Kazuhiro , Pau-Ling Chen
发明人： Tien-Chun Yang , Ming-Huei Shieh , Kurihara Kazuhiro , Pau-Ling Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/0458 , G11C16/0475 , G11C16/0491
摘要： A system and method for column selection in a non-volatile memory cell array is disclosed. A group of memory cells is arranged in a rectangular array having rows (X-dimension) and columns (Y-dimension). Within a row, the sources and drains of the memory cells are connected to form a linear chain. A common word line is coupled to each gate in the row. A separate column line is coupled to each node between adjacent memory cells of the chain. A four column Y-decoder is used to select column lines for sense operations. A voltage source is applied to two of the four column lines during the sense operation. Current on one of the column lines may be sensed to provide a measurement for read or verification.
摘要翻译：公开了一种用于非易失性存储单元阵列中的列选择的系统和方法。一组存储单元被布置成具有行（X维）和列（Y维）的矩形阵列。在一行中，存储器单元的源极和漏极被连接以形成线性链。公共字线连接到行中的每个门。单独的列线耦合到链的相邻存储器单元之间的每个节点。四列Y解码器用于选择用于感测操作的列线。在感测操作期间，将电压源施加到四列中的两条线。可以感测一列列线上的电流以提供用于读取或验证的测量。

36. 发明授权

US06859393B1 Ground structure for page read and page write for flash memory 有权
标题翻译： Flash存储器的页面读取和页面写入的接地结构
公开(公告)号：US06859393B1
公开(公告)日：2005-02-22
申请号：US10264387
申请日：2002-10-04
申请人： Tien-Chun Yang , Shigekazu Yamada , Ming-Huei Shieh , Pau-Ling Chen
发明人： Tien-Chun Yang , Shigekazu Yamada , Ming-Huei Shieh , Pau-Ling Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0491 , G11C2216/14
摘要： A ground structure for page read and page write for flash memory. An array structure of flash memory cells comprises a plurality of sectors. Each sector comprises I/O blocks plus reference arrays and an array of redundant cells. Each I/O block comprises sub I/O blocks. Each sub I/O block within an I/O block, as well as other structures including reference cells, redundant cells and edge structures is coupled to a unique ground reference signal. These unique ground reference signals may be selectively coupled to a system ground or a biased ground reference. This novel ground arrangement enables a page read operation in which one bit from each sub I/O block can be read simultaneously. In addition, one bit from each I/O block may be programmed simultaneously. Further, the ground reference voltage for cells of the array may be selectively adjusted to optimize operation.
摘要翻译：用于闪存的页面读取和页面写入的接地结构。闪存单元的阵列结构包括多个扇区。每个扇区包括I / O块加参考阵列和冗余单元阵列。每个I / O块包括子I / O块。 I / O块内的每个子I / O块以及包括参考单元，冗余单元和边缘结构的其他结构都耦合到独特的接地参考信号。这些独特的接地参考信号可以选择性地耦合到系统接地或偏置的接地参考。这种新颖的接地布置使得能够同时读取来自每个子I / O块的一个位的页面读取操作。另外，每个I / O块的一位可以同时编程。此外，可以选择性地调整阵列的单元的接地参考电压以优化操作。

37. 发明授权

US06728160B1 Path gate driver circuit 有权
标题翻译：路径驱动电路
公开(公告)号：US06728160B1
公开(公告)日：2004-04-27
申请号：US10243433
申请日：2002-09-12
申请人： Tien-Chun Yang , Kurihara Kazuhiro , Pau-Ling Chen
发明人： Tien-Chun Yang , Kurihara Kazuhiro , Pau-Ling Chen
IPC分类号： G11C800
CPC分类号： G11C16/24 , G11C7/1051 , G11C7/12
摘要： A path gate driver circuit of the present invention includes a shunt stage, a level shifter stage, a pull-up stage, and an output stage. The shunt stage has a control terminal coupled to a supply, and an input terminal coupled to a control signal path. The level shifter stage has a first control terminal coupled to the control signal path, a second control terminal coupled to an output terminal of the shunt stage, a first input terminal coupled to a boost-low supply, and a second input terminal coupled to a boost-high supply. The pull-up stage has a control terminal coupled to an output terminal of the level shifter stage, and an input terminal coupled to the boost-high supply. The output stage has a first control terminal coupled to the output terminal of the shunt stage and an output terminal of the pull-up stage, a second control terminal coupled to the control signal path a first input terminal coupled to the boost-low supply, and a second input terminal coupled to the boost-high supply. A boosted control signal is provided at the output terminal of the output stage in response to the control.
摘要翻译：本发明的路径栅极驱动电路包括分路级，电平转换级，上拉级和输出级。分流级具有耦合到电源的控制端子和耦合到控制信号路径的输入端子。电平移位器级具有耦合到控制信号路径的第一控制端，耦合到并联级的输出端的第二控制端，耦合到升压低电源的第一输入端和耦合到增加高的供应。上拉级具有耦合到电平移位器级的输出端子的控制端子和耦合到升压高电源的输入端子。输出级具有耦合到并联级的输出端和上拉级的输出端的第一控制端，耦合到控制信号路径的第二控制端，耦合到升压低电源的第一输入端，以及耦合到所述升压高电源的第二输入端子。响应于该控制，在输出级的输出端提供升压控制信号。

38. 发明授权

US09437257B2 Sensing circuit, memory device and data detecting method 有权
标题翻译：感应电路，存储器和数据检测方法
公开(公告)号：US09437257B2
公开(公告)日：2016-09-06
申请号：US13765513
申请日：2013-02-12
申请人： Tien-Chun Yang , Yue-Der Chih , Chan-Hong Chern , Tao Wen Chung
发明人： Tien-Chun Yang , Yue-Der Chih , Chan-Hong Chern , Tao Wen Chung
IPC分类号： G11C11/34 , G11C7/00 , G11C7/02 , G11C7/06 , G11C7/14 , G11C13/00
CPC分类号： G11C7/062 , G11C7/14 , G11C13/004 , G11C2207/063
摘要： A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage.
摘要翻译：感测电路包括感测电阻器，参考电阻器和比较器。比较器具有耦合到感测电阻器的第一输入端，耦合到参考电阻器的第二输入端和输出端。第一输入被配置为耦合到与存储器单元相关联的数据位线，以接收由流过感测电阻器的存储单元的单元电流引起的感测输入电压。第二输入被配置为耦合到与参考单元相关联的参考位线，以接收由参考电池流过参考电阻器的参考电流引起的感测参考电压。比较器被配置为基于感测输入电压和感测参考电压之间的比较，在输出处产生指示存储在存储器单元中的数据的逻辑状态的输出信号。

39. 发明授权

US08324960B2 Charge pump doubler 有权
标题翻译：电荷泵倍增器
公开(公告)号：US08324960B2
公开(公告)日：2012-12-04
申请号：US12849503
申请日：2010-08-03
申请人： Ming-Chieh Huang , Chan-Hong Chern , Chih-Chang Lin , Tien-Chun Yang , Yuwen Swei
发明人： Ming-Chieh Huang , Chan-Hong Chern , Chih-Chang Lin , Tien-Chun Yang , Yuwen Swei
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/07
摘要： An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor.
摘要翻译：集成电路包括第一PMOS晶体管，其中其漏极被布置成耦合到电压输出，并且其源极耦合到第二PMOS晶体管的漏极。第二PMOS晶体管的源极被布置成耦合到高电源电压。 MOS电容器的源极和漏极耦合到第一PMOS晶体管的源极。 NMOS晶体管的漏极耦合到第一PMOS晶体管的漏极。集成电路被配置为接收电压输入以产生具有高于电压输入的最大电压的电压输出。 MOS电容器的栅氧化层厚度小于第一PMOS晶体管的栅极氧化层厚度。

40. 发明授权

US08223576B2 Regulators regulating charge pump and memory circuits thereof 有权
标题翻译：调节电荷泵及其存储电路的调节器
公开(公告)号：US08223576B2
公开(公告)日：2012-07-17
申请号：US12716430
申请日：2010-03-03
申请人： Tien-Chun Yang , Chih-Chang Lin , Ming-Chieh Huang
发明人： Tien-Chun Yang , Chih-Chang Lin , Ming-Chieh Huang
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C11/4074
摘要： A regulator for regulating a charge pump is provided. The regulator includes a comparator having a first input end capable of receiving a first voltage and a second input end capable of receiving a second voltage for determining enabling or disabling the charge pump. The first voltage is associated with an output voltage of the charge pump. The second voltage is associated with an internal power voltage and a reference voltage Vref.
摘要翻译：提供了一种用于调节电荷泵的调节器。调节器包括具有能够接收第一电压的第一输入端和能够接收用于确定启动或禁用电荷泵的第二电压的第二输入端的比较器。第一电压与电荷泵的输出电压相关联。第二电压与内部电源电压和参考电压Vref相关联。

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