专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06944057B1 Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference 有权
标题翻译：使用温度依赖电压参考获得温度独立程序阈值电压分布的方法
公开(公告)号：US06944057B1
公开(公告)日：2005-09-13
申请号：US10431065
申请日：2003-05-06
申请人： Edward F. Runnion , Tien-Chun Yang , Binh Quang Le , Shigekazu Yamada , Darlene G. Hamilton , Ming-Huei Shieh , Pau-Ling Chen , Kazuhiro Kurihara
发明人： Edward F. Runnion , Tien-Chun Yang , Binh Quang Le , Shigekazu Yamada , Darlene G. Hamilton , Ming-Huei Shieh , Pau-Ling Chen , Kazuhiro Kurihara
IPC分类号： G11C16/06
CPC分类号： G11C16/3418 , G11C16/10
摘要： A method for controlling gate voltage in a memory device is described. The method includes providing a circuit that is adapted to be coupled with the memory device. The circuit is for generating a reference voltage. The method further includes utilizing the reference voltage provided by the circuit to apply a voltage at a gate of the memory device. The voltage has a value corresponding to a temperature of the memory device. The method also includes retaining a proportional relationship between the reference voltage and the temperature of the memory device, regardless of the change in the temperature of the memory device. The reference voltage provides a substantially constant programming time for the memory device regardless of the temperature of the memory device.
摘要翻译：描述了一种用于控制存储器件中的栅极电压的方法。该方法包括提供适于与存储器件耦合的电路。该电路用于产生参考电压。该方法还包括利用由电路提供的参考电压来在存储器件的栅极处施加电压。电压具有对应于存储器件的温度的值。该方法还包括保持参考电压与存储器件的温度之间的比例关系，而与存储器件的温度变化无关。参考电压为存储器件提供基本上恒定的编程时间，而与存储器件的温度无关。

2. 发明授权

US06859393B1 Ground structure for page read and page write for flash memory 有权
标题翻译： Flash存储器的页面读取和页面写入的接地结构
公开(公告)号：US06859393B1
公开(公告)日：2005-02-22
申请号：US10264387
申请日：2002-10-04
申请人： Tien-Chun Yang , Shigekazu Yamada , Ming-Huei Shieh , Pau-Ling Chen
发明人： Tien-Chun Yang , Shigekazu Yamada , Ming-Huei Shieh , Pau-Ling Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0491 , G11C2216/14
摘要： A ground structure for page read and page write for flash memory. An array structure of flash memory cells comprises a plurality of sectors. Each sector comprises I/O blocks plus reference arrays and an array of redundant cells. Each I/O block comprises sub I/O blocks. Each sub I/O block within an I/O block, as well as other structures including reference cells, redundant cells and edge structures is coupled to a unique ground reference signal. These unique ground reference signals may be selectively coupled to a system ground or a biased ground reference. This novel ground arrangement enables a page read operation in which one bit from each sub I/O block can be read simultaneously. In addition, one bit from each I/O block may be programmed simultaneously. Further, the ground reference voltage for cells of the array may be selectively adjusted to optimize operation.
摘要翻译：用于闪存的页面读取和页面写入的接地结构。闪存单元的阵列结构包括多个扇区。每个扇区包括I / O块加参考阵列和冗余单元阵列。每个I / O块包括子I / O块。 I / O块内的每个子I / O块以及包括参考单元，冗余单元和边缘结构的其他结构都耦合到独特的接地参考信号。这些独特的接地参考信号可以选择性地耦合到系统接地或偏置的接地参考。这种新颖的接地布置使得能够同时读取来自每个子I / O块的一个位的页面读取操作。另外，每个I / O块的一位可以同时编程。此外，可以选择性地调整阵列的单元的接地参考电压以优化操作。

3. 发明授权

US07142454B2 System and method for Y-decoding in a flash memory device 有权
标题翻译：闪存设备中Y解码的系统和方法
公开(公告)号：US07142454B2
公开(公告)日：2006-11-28
申请号：US10243315
申请日：2002-09-12
申请人： Tien-Chun Yang , Ming-Huei Shieh , Kurihara Kazuhiro , Pau-Ling Chen
发明人： Tien-Chun Yang , Ming-Huei Shieh , Kurihara Kazuhiro , Pau-Ling Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/0458 , G11C16/0475 , G11C16/0491
摘要： A system and method for column selection in a non-volatile memory cell array is disclosed. A group of memory cells is arranged in a rectangular array having rows (X-dimension) and columns (Y-dimension). Within a row, the sources and drains of the memory cells are connected to form a linear chain. A common word line is coupled to each gate in the row. A separate column line is coupled to each node between adjacent memory cells of the chain. A four column Y-decoder is used to select column lines for sense operations. A voltage source is applied to two of the four column lines during the sense operation. Current on one of the column lines may be sensed to provide a measurement for read or verification.
摘要翻译：公开了一种用于非易失性存储单元阵列中的列选择的系统和方法。一组存储单元被布置成具有行（X维）和列（Y维）的矩形阵列。在一行中，存储器单元的源极和漏极被连接以形成线性链。公共字线连接到行中的每个门。单独的列线耦合到链的相邻存储器单元之间的每个节点。四列Y解码器用于选择用于感测操作的列线。在感测操作期间，将电压源施加到四列中的两条线。可以感测一列列线上的电流以提供用于读取或验证的测量。

4. 发明授权

US06819591B1 Method for erasing a memory sector in virtual ground architecture with reduced leakage current 有权
标题翻译：在漏电流减少的情况下擦除虚拟地面架构中的存储器区域的方法
公开(公告)号：US06819591B1
公开(公告)日：2004-11-16
申请号：US10762071
申请日：2004-01-20
申请人： Kazuhiro Kurihara , Ming-Huei Shieh , Santosh Yachareni , Pau-Ling Chen
发明人： Kazuhiro Kurihara , Ming-Huei Shieh , Santosh Yachareni , Pau-Ling Chen
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C16/0491
摘要： An exemplary memory sector erase method comprises the steps of pre-programming a first bit and a second bit of a plurality of core memory cells of a plurality of memory blocks of a target memory sector, pre-programming one of a third bit and a fourth bit of a first neighboring memory cell adjacent to the target memory sector, and erasing the first bit and the second bit of the plurality of core memory cells of the plurality of memory blocks. According to another embodiment, the method further comprises programming the one of the third bit and the fourth bit of the first neighboring memory cell after the erasing step.
摘要翻译：示例性存储器扇区擦除方法包括以下步骤：对目标存储器扇区的多个存储器块的多个核心存储器单元的第一位和第二位进行预编程，预编程第三位和第四与目标存储器扇区相邻的第一相邻存储单元的位，以及擦除多个存储块中的多个存储单元的第一位和第二位。根据另一实施例，该方法还包括在擦除步骤之后编程第一相邻存储器单元的第三位和第四位之一。

5. 发明授权

US06744666B1 Method and system to minimize page programming time for flash memory devices 有权
标题翻译：方法和系统，最大程度地减少闪存设备的页面编程时间
公开(公告)号：US06744666B1
公开(公告)日：2004-06-01
申请号：US10243792
申请日：2002-09-12
申请人： Santosh Yachareni , Kazuhiro Kurihara , Ming-Huei Shieh , Pau-Ling Chen
发明人： Santosh Yachareni , Kazuhiro Kurihara , Ming-Huei Shieh , Pau-Ling Chen
IPC分类号： G11C1134
CPC分类号： G11C16/10 , G11C2216/14 , G11C2216/16
摘要： Embodiments of the present invention are directed to a method and system to minimize page programming time for page programmable memory devices. In one embodiment, the present invention comprises program logic that programs a page programmable memory device with a plurality of words during a page programming cycle and a detector coupled to the program logic that identifies a particular word in that plurality of words which does not require programming. When the detector identifies a particular word which does not require programming, it sends an indication to the program logic component which, in response to the signal, reduces the length of the page programming cycle.
摘要翻译：本发明的实施例涉及一种使页面可编程存储器件的页面编程时间最小化的方法和系统。在一个实施例中，本发明包括在页面编程周期期间用多个单词编程页面可编程存储器件的程序逻辑和耦合到程序逻辑的检测器，该程序逻辑识别出不需要编程的多个单词中的特定单词。当检测器识别不需要编程的特定字时，它向程序逻辑组件发送指示，该程序逻辑组件响应于该信号减少了页面编程周期的长度。

6. 发明授权

US06735114B1 Method of improving dynamic reference tracking for flash memory unit 有权
标题翻译：改进闪存单元动态参考跟踪的方法
公开(公告)号：US06735114B1
公开(公告)日：2004-05-11
申请号：US10357879
申请日：2003-02-04
申请人： Darlene G. Hamilton , Eric M. Ajimine , Ming-Huei Shieh , Lee Cleveland , Edward F. Runnion , Mark W. Randolph , Sameer S. Haddad
发明人： Darlene G. Hamilton , Eric M. Ajimine , Ming-Huei Shieh , Lee Cleveland , Edward F. Runnion , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C1604
CPC分类号： G11C16/3418 , G11C16/0475 , G11C16/28
摘要： A method of programming a memory unit having a plurality of dual cell core memory devices and at least one dual cell dynamic reference device. The memory unit is subjected to an erase configuration operation such that each cell of the core memory devices is in a blank state and such that a threshold voltage of the at least one dynamic reference device is less than a charged program level threshold voltage. Thereafter, the at least one dynamic reference and the core memory devices are programmed using a page programming routine.
摘要翻译：一种编程具有多个双单元核心存储器件和至少一个双单元动态参考器件的存储器单元的方法。对存储器单元进行擦除配置操作，使得核心存储器件的每个单元处于空白状态，并且使得至少一个动态参考器件的阈值电压小于充电的程序电平阈值电压。此后，使用页面编程例程对至少一个动态参考和核心存储器设备进行编程。

7. 发明授权

US5280445A Multi-dimensional memory cell using resonant tunneling diodes 失效
标题翻译：使用谐振隧道二极管的多维存储单元
公开(公告)号：US5280445A
公开(公告)日：1994-01-18
申请号：US940226
申请日：1992-09-03
申请人： Ming-Huei Shieh , Hung C. Lin
发明人： Ming-Huei Shieh , Hung C. Lin
IPC分类号： G11C11/56 , G11C5/06
CPC分类号： B82Y10/00 , G11C11/56 , G11C2211/5614
摘要： A number of resonant tunneling diodes are connected in series with a resistor, a current source or a load device. A bit line is connected to every joint between any two devices through a switch. When properly biased, there can be (N+1).sup.m number of stable quantized operating points which are represented by a combination of m variables (of either voltage or current, where N is the number of peaks of the folding I-V characteristic and m is the number of bit lines. The m bit lines can write in (N+1).sup.m different combinations of inputs. During reading, the quantized voltage (or current) at each bit line is sensed. The number of stable states can be doubled by changing the polarity of the power supply.
摘要翻译：多个谐振隧道二极管与电阻器，电流源或负载装置串联连接。通过开关将位线连接到任何两个设备之间的每个接头。当适当偏置时，可以有（N + 1）m个稳定的量化工作点，它们由m个变量（电压或电流的组合）表示，其中N是折叠IV特性的峰值数，m是位线数，m位线可以写入（N + 1）m个不同的输入组合，在读取期间，检测每个位线处的量化电压（或电流），稳定状态的数量可以加倍改变电源的极性。

8. 发明授权

US08665651B1 Reference cell circuit and method of producing a reference current 有权
标题翻译：参考电路和产生参考电流的方法
公开(公告)号：US08665651B1
公开(公告)日：2014-03-04
申请号：US13610448
申请日：2012-09-11
申请人： Chi-Shun Lin , Seow-Fong Lim , Ming-Huei Shieh
发明人： Chi-Shun Lin , Seow-Fong Lim , Ming-Huei Shieh
IPC分类号： G11C11/34 , G11C16/06 , G11C7/00 , G11C7/02
CPC分类号： G11C7/14 , G11C5/147 , G11C16/28
摘要： The present invention discloses a reference cell circuit which is applied to a non-volatile memory. The reference cell circuit includes a reference cell array, a first current mirror circuit, and a second current mirror circuit. The reference cell array includes at least one row of floating gate transistors. The first current mirror circuit is arranged to generate a mirror current according to a reference current generated by the reference cell array. The second current mirror circuit is arranged to receive the mirror current and generate an adjusted reference current according to the mirror current and a selected one of a plurality of enable signals, wherein the plurality of enable signals correspond to a plurality operations of the non-volatile memory and the adjusted reference current is arranged to determine logical state of a plurality of memory cells of the non-volatile memory.
摘要翻译：本发明公开了一种应用于非易失性存储器的参考单元电路。参考单元电路包括参考单元阵列，第一电流镜电路和第二电流镜电路。参考单元阵列包括至少一行浮置栅极晶体管。第一电流镜电路被布置成根据由参考单元阵列产生的参考电流产生镜电流。第二电流镜电路被布置成接收反射镜电流并且根据镜电流和多个使能信号中的选定一个产生调整的参考电流，其中多个使能信号对应于非易失性的多个操作存储器和经调整的参考电流被布置成确定非易失性存储器的多个存储单元的逻辑状态。

9. 发明申请

US20080117678A1 MEMORY WITH A CORE-BASED VIRTUAL GROUND AND DYNAMIC REFERENCE SENSING SCHEME 有权
标题翻译：具有基于核心的虚拟地面和动态参考感测方案的记忆
公开(公告)号：US20080117678A1
公开(公告)日：2008-05-22
申请号：US12017693
申请日：2008-01-22
申请人： Ming-Huei Shieh , Kazuhiro Kurihara
发明人： Ming-Huei Shieh , Kazuhiro Kurihara
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/28 , G11C11/5642 , G11C11/5671 , G11C16/0475 , G11C2211/5634
摘要： A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408, 410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising one cell (182) of the first reference array (408) and a corresponding cell (184) of the second reference array (410) are read and averaged to provide a reference voltage for reading a data array(s).
摘要翻译：一种具有在存储器核心（401）上制造的双位动态参考架构（408,410）的基于核心的多位存储器（400）。在存储器核心（401）上制造第一参考阵列（408）和第二参考阵列（410），使得包括第一参考阵列（408）的一个单元（182）的参考单元对（185）和相应的对第二参考阵列（410）的单元（184）进行读取和平均以提供用于读取数据阵列的参考电压。

10. 发明授权

US06118702A Source bias compensation for page mode read operation in a flash memory device 有权
标题翻译：闪存设备中页面模式读取操作的源偏置补偿
公开(公告)号：US06118702A
公开(公告)日：2000-09-12
申请号：US421151
申请日：1999-10-19
申请人： Ming-Huei Shieh , Bhimachar Venkatesh
发明人： Ming-Huei Shieh , Bhimachar Venkatesh
IPC分类号： G11C5/14 , G11C16/28 , G11C16/06
CPC分类号： G11C16/28 , G11C5/14
摘要： A page mode memory senses a large number of bits simultaneously. The associated read current creates a source bias in the core cells which alters the sense margin at the sense amplifier. To address this problem, a memory integrated circuit (100) includes an array (102) of core cells, each core cell having a ground node (220, 222, 224). A ground line (230) couples the ground node of each core cell to a ground potential (Vss) and establishes a variable parasitic potential between the ground node and Vss. For sensing the data state of the core cells, a reference core cell (252) matches the array core cells and has a reference ground node (262). A circuit element (256) is coupled between the reference ground node and Vss to establish a variable reference potential to match the variable parasitic potential.
摘要翻译：页面模式存储器同时感测大量的位。关联的读取电流在核心单元中产生源偏置，其改变感测放大器处的感测边缘。为了解决这个问题，存储器集成电路（100）包括核心单元的阵列（102），每个核心单元具有接地节点（220,222,224）。接地线（230）将每个核心单元的接地节点耦合到地电位（Vss），并在接地节点和Vss之间建立可变的寄生电位。为了感测核心单元的数据状态，参考核心单元（252）与阵列核心单元匹配并具有参考接地节点（262）。电路元件（256）耦合在参考接地节点和Vss之间以建立可变参考电位以匹配可变寄生电位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式