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1. 发明授权

US08736351B2 Negative charge pump 有权
标题翻译：负电荷泵
公开(公告)号：US08736351B2
公开(公告)日：2014-05-27
申请号：US13005643
申请日：2011-01-13
申请人： Tien-Chun Yang , Yvonne Lin , Ming-Chieh Huang
发明人： Tien-Chun Yang , Yvonne Lin , Ming-Chieh Huang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K5/15013 , H02M3/07 , H02M2003/071
摘要： A charge pump includes a first node configured to receive a first voltage and a second node coupled to the first node through a first transistor. The second node is configured to output a voltage having a greater voltage magnitude than the first voltage. A first capacitor is coupled to a third node, and a fourth node is configured to receive a first clock signal. The third node is disposed between a drain of the first transistor and the fourth node. A leaky circuit device is coupled in parallel with the first capacitor for draining charges of a first polarity away from the second node.
摘要翻译：电荷泵包括被配置为通过第一晶体管接收耦合到第一节点的第一电压和第二节点的第一节点。第二节点被配置为输出具有比第一电压更大的电压幅度的电压。第一电容器耦合到第三节点，并且第四节点被配置为接收第一时钟信号。第三节点设置在第一晶体管的漏极和第四节点之间。泄漏电路装置与第一电容器并联耦合，用于将第一极性的电荷从第二节点排出。

2. 发明授权

US08427229B2 Integrated circuits with bi-directional charge pumps 有权
标题翻译：具有双向电荷泵的集成电路
公开(公告)号：US08427229B2
公开(公告)日：2013-04-23
申请号：US13038519
申请日：2011-03-02
申请人： Yvonne Lin , Tien-Chun Yang
发明人： Yvonne Lin , Tien-Chun Yang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/02 , G11C5/145 , H02M3/07
摘要： Integrated circuits such as memory arrays are coupled to a bi-directional charge pump that includes an input circuit and output circuit, and one or more pump stages coupled between the input circuit and the output circuit of the bi-directional charge pump. The output circuit includes a diode having an input and output and a transistor connected to the output of the diode and a ground potential. The input of the diode is electrically connected to the pump stages in a configuration that allows the charge pump to apply a positive or negative voltage to the memory array or other load.
摘要翻译：诸如存储器阵列的集成电路耦合到双向电荷泵，其包括输入电路和输出电路，以及耦合在双向电荷泵的输入电路和输出电路之间的一个或多个泵级。输出电路包括具有输入和输出的二极管和连接到二极管的输出和地电位的晶体管。二极管的输入以允许电荷泵将正或负电压施加到存储器阵列或其它负载的配置电连接到泵级。

3. 发明申请

US20120182058A1 NEGATIVE CHARGE PUMP 有权
标题翻译：负电荷泵
公开(公告)号：US20120182058A1
公开(公告)日：2012-07-19
申请号：US13005643
申请日：2011-01-13
申请人： Tien-Chun Yang , Yvonne Lin , Ming-Chieh Huang
发明人： Tien-Chun Yang , Yvonne Lin , Ming-Chieh Huang
IPC分类号： H03K3/00 , G05F1/10
CPC分类号： H03K5/15013 , H02M3/07 , H02M2003/071
摘要： A charge pump includes a first node configured to receive a first voltage and a second node coupled to the first node through a first transistor. The second node is configured to output a voltage having a greater voltage magnitude than the first voltage. A first capacitor is coupled to a third node, and a fourth node is configured to receive a first clock signal. The third node is disposed between a drain of the first transistor and the fourth node. A leaky circuit device is coupled in parallel with the first capacitor for draining charges of a first polarity away from the second node.
摘要翻译：电荷泵包括被配置为通过第一晶体管接收耦合到第一节点的第一电压和第二节点的第一节点。第二节点被配置为输出具有比第一电压更大的电压幅度的电压。第一电容器耦合到第三节点，并且第四节点被配置为接收第一时钟信号。第三节点设置在第一晶体管的漏极和第四节点之间。泄漏电路装置与第一电容并联耦合，用于从第二节点排出第一极性的电荷。

4. 发明授权

US08908434B2 Operating methods of flash memory and decoding circuits thereof 有权
标题翻译：闪存及其解码电路的操作方法
公开(公告)号：US08908434B2
公开(公告)日：2014-12-09
申请号：US13021381
申请日：2011-02-04
申请人： Yvonne Lin , Tien-Chun Yang
发明人： Yvonne Lin , Tien-Chun Yang
IPC分类号： G11C16/00 , G11C16/14 , G11C16/12 , H01L27/15 , G11C16/04 , G11C16/32
CPC分类号： G11C16/14 , G11C16/0408 , G11C16/12 , G11C16/32 , H01L27/15
摘要： A FLASH memory cell includes a control gate over a floating gate over a substrate. A wall line and an erase gate each is disposed adjacent to a respective sidewall of the control gate. A first source/drain (S/D) region is disposed in the substrate and adjacent to a sidewall of the wall line. A second S/D region is disposed in the substrate and adjacent to the sidewall of the floating gate. A method of operating the FLASH memory cell includes applying a first voltage level to the control gate. A second voltage level is applied to the word line. The second voltage level is lower than the first voltage level. A third voltage level is applied to the first S/D region. A fourth voltage level is applied to the second S/D region. The fourth voltage level is higher than the third voltage level. The erase gate is electrically floating.
摘要翻译：闪存单元包括位于衬底上的浮动栅极上的控制栅极。壁线和擦除栅极分别邻近控制栅极的相应侧壁设置。第一源极/漏极（S / D）区域设置在衬底中并且邻近壁线的侧壁。第二S / D区域设置在衬底中并且与浮动栅极的侧壁相邻。一种操作闪速存储单元的方法包括将第一电压电平施加到控制栅极。第二个电压电平被施加到字线。第二电压电平低于第一电压电平。第三电压电平施加到第一S / D区域。第四电压电平施加到第二S / D区域。第四电压电平高于第三电压电平。擦除门电浮动。

5. 发明授权

US08710908B2 Charge pump and method of biasing deep N-well in charge pump 有权
标题翻译：电荷泵和偏置电荷泵深N阱的方法
公开(公告)号：US08710908B2
公开(公告)日：2014-04-29
申请号：US13015906
申请日：2011-01-28
申请人： Yvonne Lin , Tien-Chun Yang
发明人： Yvonne Lin , Tien-Chun Yang
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , H02M3/073 , H02M2003/075
摘要： A charge pump has at least one charge pump stage. Each charge pump stage includes at least one NMOS device. The at least one NMOS device has a deep N-well (DNW), and is coupled to at least one capacitor, an input node, and an output node. The input node is arranged to receive an input signal. The at least one capacitor is arranged to store electrical charges. The charge pump stage is configured to supply the electrical charges to the output node, and the DNW is arranged to float for a positive pump operation.
摘要翻译：电荷泵具有至少一个电荷泵级。每个电荷泵级包括至少一个NMOS器件。至少一个NMOS器件具有深N阱（DNW），并且耦合到至少一个电容器，输入节点和输出节点。输入节点被布置成接收输入信号。至少一个电容器被布置成存储电荷。电荷泵级被配置为将电荷提供给输出节点，并且DNW被布置为浮动用于正泵操作。

6. 发明授权

US08238178B2 Redundancy circuits and operating methods thereof 有权
标题翻译：冗余电路及其操作方法
公开(公告)号：US08238178B2
公开(公告)日：2012-08-07
申请号：US12704676
申请日：2010-02-12
申请人： Tien-Chun Yang , Yue-Der Chih , Shang-Hsuan Liu
发明人： Tien-Chun Yang , Yue-Der Chih , Shang-Hsuan Liu
IPC分类号： G11C7/00 , G11C11/34
CPC分类号： G11C29/04 , G11C16/0408 , G11C16/0483 , G11C29/808
摘要： A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third IO interface and a fourth memory array coupled with a fourth TO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays.
摘要翻译：存储器电路包括第一组存储器阵列，其包括与第一输入/输出（IO）接口耦合的第一存储器阵列和与第二IO接口耦合的第二存储器阵列。第二组存储器阵列包括与第三IO接口耦合的第三存储器阵列和与第四TO接口耦合的第四存储器阵列。多个冗余位线包括被配置用于选择性地修复第一组存储器阵列的至少一个第一冗余位线和被配置用于选择性地修复第二组存储器阵列的至少一个第二冗余位线。

7. 发明申请

US20080144390A1 Drain voltage regulator 有权
公开(公告)号：US20080144390A1
公开(公告)日：2008-06-19
申请号：US11639936
申请日：2006-12-15
申请人： Yonggang Wu , Nian Yang , Tien-Chun Yang
发明人： Yonggang Wu , Nian Yang , Tien-Chun Yang
IPC分类号： G11C16/12 , G11C7/12
CPC分类号： G11C7/16 , G11C5/147 , G11C7/12
摘要： A voltage regulator comprises resistor elements that mitigate variations in a program voltage (VPROG). In particular, the resistors allow copies of the voltage regulator to be fabricated more consistently across a semiconductor substrate. As such, variations in respective program voltages applied to different bitlines of a memory arrangement are mitigated. This mitigates yield loss as more devices perform as desired, thus necessitating fewer discards.

8. 发明授权

US06859748B1 Test structure for measuring effect of trench isolation on oxide in a memory device 有权
标题翻译：沟槽隔离对存储器件中氧化物的影响的测试结构
公开(公告)号：US06859748B1
公开(公告)日：2005-02-22
申请号：US10190420
申请日：2002-07-03
申请人： Nian Yang , Zhigang Wang , Tien-Chun Yang
发明人： Nian Yang , Zhigang Wang , Tien-Chun Yang
IPC分类号： H01L23/544 , G01R27/29 , G01S31/00
CPC分类号： H01L22/34
摘要： An apparatus for measuring effects of isolation processes (280) on an oxide layer (286) in a memory device (255) is described. In one embodiment, the apparatus comprises a structure (110) comprised of an array (110c) of memory devices (255). A testing unit (120) is coupled with the structure (110). The testing unit (120) is for performing various electrical tests on the array (110c) of memory devices (255). The testing unit (120) is also for providing data regarding each memory device (255) in the array (110c) of memory devices (255). An analyzer (120) is coupled with the structure (110) for analyzing results of the various electrical tests. This determines the condition of the oxide layer (286) of each memory device (255) in the array of memory devices (110c).
摘要翻译：描述了用于测量隔离过程（280）对存储器件（255）中的氧化物层（286）的影响的装置。在一个实施例中，该装置包括由存储器件（255）的阵列（110c）组成的结构（110）。测试单元（120）与结构（110）耦合。测试单元（120）用于在存储器件（255）的阵列（110c）上执行各种电测试。测试单元（120）还用于提供关于存储器件（255）的阵列（110c）中的每个存储器件（255）的数据。分析器（120）与结构（110）耦合，用于分析各种电气测试的结果。这决定了存储器件阵列（110c）中每个存储器件（255）的氧化物层（286）的状态。

9. 发明授权

US06825684B1 Hot carrier oxide qualification method 失效
标题翻译：热载体氧化物鉴定方法
公开(公告)号：US06825684B1
公开(公告)日：2004-11-30
申请号：US10165879
申请日：2002-06-10
申请人： Hyeon-Seag Kim , Amit P. Marathe , Nian Yang , Tien-Chun Yang
发明人： Hyeon-Seag Kim , Amit P. Marathe , Nian Yang , Tien-Chun Yang
IPC分类号： G01R3100
CPC分类号： G01R31/287 , H01L22/20
摘要： A method of generating a lifetime projection for semiconductor devices is disclosed. The disclosed method includes collecting lifetime information from a plurality of semiconductor devices at more than one stress condition. The method also includes determining the median lifetime for semiconductor devices at each of the stress conditions. Further, the method includes calculating a lifetime at each stress condition at which a predetermined percentage of the devices will exceed and extrapolating the lifetime for devices used at operating conditions.
摘要翻译：公开了一种为半导体器件生成寿命投影的方法。所公开的方法包括在多于一个应力条件下从多个半导体器件收集寿命信息。该方法还包括在每个应力条件下确定半导体器件的中值寿命。此外，该方法包括计算在预定百分比的装置将超过的每个应力条件下的寿命，并且对在操作条件下使用的装置的寿命进行推断。

10. 发明授权

US06759295B1 METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A GATE CURRENT MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND DEVICE THEREBY FORMED 有权
标题翻译：使用栅极电流测量技术确定闪存隔离结构之间的活动区域宽度的方法，用于制造闪速存储器半导体器件及其形成的器件
公开(公告)号：US06759295B1
公开(公告)日：2004-07-06
申请号：US10224737
申请日：2002-08-20
申请人： Tien-Chun Yang , Nian Yang , Zhigang Wang
发明人： Tien-Chun Yang , Nian Yang , Zhigang Wang
IPC分类号： H01I21336
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method of determining the active region width (10) of an active region (4) by measuring the respective gate currents (Ig,100, Ig,100′, Ig,100″) of respective composite capacitance structures (100, 100′, 100″), respectively comprising at least one capacitor element (16, 17, 18; 16′, 17′, 18″; 16″, 17″, 18″) having respective predetermined widths (Wi) for fabricating a flash memory semiconductor device, and a device thereby fabricated. The present method also comprises plotting the respective gate currents (Ig,100, Ig,100 ′, Ig,100″) as a quasi-linear function (IW) of the respective predetermined widths (Wi), extrapolating a calibration term (WI=0) from the quasi-linear function (IW), and subtracting the calibration term (WIg=0) from the respective predetermined widths (Wi) to define and constrain the active region width (10) for facilitating device fabrication.
摘要翻译：通过测量各个复合电容结构（100,100'）的相应栅极电流（Ig，100，Ig，100'，Ig，100“）来确定有源区（4）的有源区宽度（10）的方法，，100“），分别包括至少一个具有相应预定宽度（Wi）的电容器元件（16,17,18; 16'，17”，18“，16”，17“，18”），制造闪速存储器半导体器件，以及由此制造的器件。本方法还包括将相应的栅极电流（Ig，100，Ig，100'，Ig，100“）绘制为各个预定宽度（Wi）的准线性函数（IW），外推校准项 = 0），并从相应的预定宽度（Wi）减去校准项（WIg = 0），以限定和约束有源区宽度（10）以便于器件制造。

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