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31. 发明授权

US07276249B2 Nanoparticulate fibrate formulations 有权
标题翻译：纳米颗粒贝特类制剂
公开(公告)号：US07276249B2
公开(公告)日：2007-10-02
申请号：US10444066
申请日：2003-05-23
申请人： Tuula Ryde , Evan E. Gustow , Stephen B. Ruddy , Rajeev Jain , Rakesh Patel , Michael John Wilkins
发明人： Tuula Ryde , Evan E. Gustow , Stephen B. Ruddy , Rajeev Jain , Rakesh Patel , Michael John Wilkins
IPC分类号： A61K9/48 , A61K9/20 , A61K9/14
CPC分类号： A61K31/19 , A61K9/145 , A61K9/146 , A61K9/2077 , A61K31/14 , A61K31/216 , A61K45/06 , Y10T428/29 , A61K2300/00
摘要： The present invention is directed to fibrate compositions having improved pharmacokinetic profiles and reduced fed/fasted variability. The fibrate particles of the composition have an effective average particle size of less than about 2000 nm.
摘要翻译：本发明涉及具有改善的药代动力学特征和降低的进食/禁食变异性的贝特类组合物。组合物的贝特类颗粒具有小于约2000nm的有效平均粒度。

32. 发明申请

US20070154569A1 Use of nitrite salts for the treatment of cardiovascular conditions 有权
标题翻译：使用亚硝酸盐治疗心血管疾病
公开(公告)号：US20070154569A1
公开(公告)日：2007-07-05
申请号：US10563683
申请日：2004-07-09
申请人： Mark Gladwin , Alan Schechter , David Lefer , Rakesh Patel , Christian Hunter , Gordon Power , Daniel Kim-Shapiro , Ryszard Pluta , Edward Oldfield , Richard Cannon
发明人： Mark Gladwin , Alan Schechter , David Lefer , Rakesh Patel , Christian Hunter , Gordon Power , Daniel Kim-Shapiro , Ryszard Pluta , Edward Oldfield , Richard Cannon
IPC分类号： A61K33/00 , A61P9/00 , A01N59/00 , A61P11/00
CPC分类号： A61K33/00 , A61K45/06 , A61K2300/00
摘要： It has been surprisingly discovered that administration of nitrite to subjects causes a reduction in blood pressure and an increase in blood flow to tissues. The effect is particularly beneficial, for example, to tissues in regions of low oxygen tension. This discovery provides useful treatments to regulate a subject's blood pressure and blood flow, for example, by the administration of nitrite salts. Provided herein are methods of administering a pharmaceutically-acceptable nitrite salt to a subject, for treating, preventing or ameliorating a condition selected from: (a) ischemia-reperfusion injury (e.g., hepatic or cardiac or brain ischemia-reperfusion injury); (b) pulmonary hypertension (e.g., neonatal pulmonary hypertension); or (c) cerebral artery vasospasm.
摘要翻译：令人惊讶地发现，向受试者施用亚硝酸盐导致血压降低和对组织的血流量的增加。该效果特别有利于例如低氧张力区域中的组织。该发现提供了有用的治疗方法来调节受试者的血压和血流量，例如通过施用亚硝酸盐。本文提供了向受试者施用药学上可接受的亚硝酸盐，用于治疗，预防或改善选自以下的病症的方法：（a）缺血再灌注损伤（例如肝脏或心脏或脑缺血 - 再灌注损伤）; （b）肺动脉高压（如新生儿肺动脉高压）; 或（c）大脑动脉血管痉挛。

33. 发明申请

US20070011370A1 Multiple data rates in programmable logic device serial interface 有权
标题翻译：可编程逻辑器件串行接口中的多个数据速率
公开(公告)号：US20070011370A1
公开(公告)日：2007-01-11
申请号：US11177007
申请日：2005-07-08
申请人： Ramanand Venkata , Rakesh Patel , Chong Lee
发明人： Ramanand Venkata , Rakesh Patel , Chong Lee
IPC分类号： G06F13/38
CPC分类号： H03K19/17744
摘要： A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably lower than the second range of data rates and preferably the first number of channels is higher than the second number of channels which preferably is 1. For backward compatibility with existing devices, the first number of channels in each interface preferably is four. Each channel preferably includes a physical medium attachment module and a physical coding sublayer module. Each of the higher-speed channels in the second number of channels preferably also includes a clock management unit, while the lower-speed channels in the first number of channels preferably share one or more clock management units.
摘要翻译：用于可编程逻辑器件的串行接口通过提供支持第一范围的数据速率的第一数量的通道和支持第二数据速率范围的第二数量的通道来支持宽范围的数据速率。数据速率的第一范围优选地低于数据速率的第二范围，并且优选地，第一数量的信道高于优选为1的信道的第二数量。为了与现有设备的向后兼容，每个信道中的第一数量的信道界面最好是四。每个通道优选地包括物理介质连接模块和物理编码子层模块。第二数量的频道中的每一个较高频道优选地还包括时钟管理单元，而第一数量的频道中的较低速频道优选地共享一个或多个时钟管理单元。

34. 发明申请

US20060119382A1 Apparatus and methods for adjusting performance characteristics of programmable logic devices 审中-公开
标题翻译：用于调整可编程逻辑器件性能特性的装置和方法
公开(公告)号：US20060119382A1
公开(公告)日：2006-06-08
申请号：US11006420
申请日：2004-12-07
申请人： Sergey Shumarayev , Rakesh Patel
发明人： Sergey Shumarayev , Rakesh Patel
IPC分类号： H03K19/003
CPC分类号： H03K19/0016 , G06F17/5054 , G06F2217/84 , H01L2924/0002 , H03K19/00369 , H03K19/17732 , H03K19/17748 , H03K19/17784 , H03K19/17792 , H01L2924/00
摘要： A programmable logic device (PLD) includes a circuit that controls a supply voltage of at least a portion of the circuitry within the PLD (such as a block, a sub-block, or a region). The circuit also filters noise within the PLD. Controlling the supply voltage allows trading off various performance characteristics, such as speed and power consumption.
摘要翻译：可编程逻辑器件（PLD）包括控制PLD（例如块，子块或区域）内的电路的至少一部分的电源电压的电路。该电路还对PLD内的噪声进行滤波。控制电源电压可以消除各种性能特性，如速度和功耗。

35. 发明授权

US06989689B2 Interconnection and input/output resources for programmable logic integrated circuit devices 失效
公开(公告)号：US06989689B2
公开(公告)日：2006-01-24
申请号：US10852858
申请日：2004-05-24
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
IPC分类号： H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

36. 发明申请

US20060012394A1 Programmable logic devices with multi-standard byte synchronization and channel alignment for communication 有权
公开(公告)号：US20060012394A1
公开(公告)日：2006-01-19
申请号：US11189209
申请日：2005-07-26
申请人： Ramanand Venkata , Chong Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong Lee , Rakesh Patel
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H04J3/1617 , H04J2203/0082 , H04J2203/0094
摘要： A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

37. 发明授权

US06894533B2 Interconnection and input/output resources for programmable logic integrated circuit devices 有权
标题翻译：可编程逻辑集成电路器件的互连和输入/输出资源
公开(公告)号：US06894533B2
公开(公告)日：2005-05-17
申请号：US10458431
申请日：2003-06-09
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
IPC分类号： G06F7/50 , G06F7/506 , H03K19/173 , H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.
摘要翻译：可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

38. 发明授权

US06867616B1 Programmable logic device serial interface having dual-use phase-locked loop circuitry 有权
标题翻译：具有双用途锁相环电路的可编程逻辑器件串行接口
公开(公告)号：US06867616B1
公开(公告)日：2005-03-15
申请号：US10455773
申请日：2003-06-04
申请人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
IPC分类号： H03K19/177 , H03K19/173 , H03D3/24
CPC分类号： H03K19/17736 , H03K19/1774 , H03K19/17744
摘要： In a programmable logic device (“PLD”), a serial interface incorporating phase-locked loops (“PLLs”) is provided with connections that allow one or more of the PLLs to be used as general purpose PLLs in the PLD. The connections include conductors to allow reference clock signals from the PLD logic core, or from outside the PLL, to be used by the PLLS, as well as conductors that allow the PLD core to control the phases of the PLLs. For some of the PLLs, conductors to allow the PLL output clock to be used by the PLD are also provided, where such output conductors do not normally exist in such a serial interface.
摘要翻译：在可编程逻辑器件（“PLD”）中，集成了锁相环（“PLL”）的串行接口具有允许一个或多个PLL用作PLD中的通用PLL的连接。这些连接包括允许来自PLD逻辑核心或PLL外部的参考时钟信号由PLLS使用的导体以及允许PLD内核控制PLL相位的导体。对于一些PLL，还提供允许PLD使用PLL输出时钟的导体，其中这种输出导体通常不存在于这种串行接口中。

39. 发明授权

US06366120B1 Interconnection resources for programmable logic integrated circuit devices 有权
标题翻译：可编程逻辑集成电路器件的互连资源
公开(公告)号：US06366120B1
公开(公告)日：2002-04-02
申请号：US09517146
申请日：2000-03-02
申请人： James Schleicher , James Park , Sergey Shumarayev , Bruce Pedersen , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
发明人： James Schleicher , James Park , Sergey Shumarayev , Bruce Pedersen , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
IPC分类号： H03K190177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/17792
摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.
摘要翻译：可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

40. 发明授权

US6154059A High performance output buffer 有权
标题翻译：高性能输出缓冲器
公开(公告)号：US6154059A
公开(公告)日：2000-11-28
申请号：US199705
申请日：1998-11-24
申请人： Sammy Cheung , John Lam , Rakesh Patel , Tony Ngai
发明人： Sammy Cheung , John Lam , Rakesh Patel , Tony Ngai
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/00361
摘要： An output buffer has internal circuitry connected between an input node and an output node. The internal circuitry includes a quiet voltage supply connected to a first set of transistors of the internal circuitry and a noisy voltage supply connected to a second set of transistors of the internal circuitry. The noisy voltage supply is at a voltage level higher than the quiet voltage supply. The first set of transistors and the second set of transistors provide isolation between the noisy voltage supply and the quiet voltage supply. The first set of transistors and the second set of transistors also provide complete digital high and low internal signal levels by using at least one transistor operative to supplement the complete shut-off and turn-on of transistors of the first set of transistors and the second set of transistors. The output buffer also features a ground bounce circuit, a slew rate control circuit, a transition accelerator circuit, a Personal Computer Interface (PCI) compatibility circuit, and a PCI control circuit.
摘要翻译：输出缓冲器具有连接在输入节点和输出节点之间的内部电路。内部电路包括连接到内部电路的第一组晶体管的静音电压源和连接到内部电路的第二组晶体管的噪声电压源。嘈杂的电源电压处于高于静态电源的电压电平。第一组晶体管和第二组晶体管提供噪声电压源和安静电源之间的隔离。第一组晶体管和第二组晶体管还通过使用至少一个晶体管提供完整的数字高和低内部信号电平，该晶体管可操作地补充第一组晶体管的晶体管的完全截止和导通，第二组晶体管的第二组一组晶体管。输出缓冲器还具有接地反弹电路，压摆率控制电路，转换加速器电路，个人计算机接口（PCI）兼容性电路和PCI控制电路。

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