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31. 发明申请

US20070252172A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070252172A1
公开(公告)日：2007-11-01
申请号：US11741305
申请日：2007-04-27
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L31/00
CPC分类号： H01L29/7828 , H01L29/0623 , H01L29/0653 , H01L29/0847 , H01L29/1033 , H01L29/1608 , H01L29/267 , H01L29/36 , H01L29/4236 , H01L29/45 , H01L29/456 , H01L29/8618
摘要： A semiconductor device, includes: 1) a semiconductor base having a first face; 2) a hetero semiconductor region configured to contact the first face of the semiconductor base and different from the semiconductor base in band gap, the semiconductor base and the hetero semiconductor region defining therebetween a junction part in the hetero semiconductor region, a concentration of an impurity introduced in at least a first certain region including the junction part being less than or equal to a solid solution limit to a semiconductor material included in the hetero semiconductor region; 3) a gate electrode formed, via a gate insulation film, in a certain position adjacent to the junction part; 4) a source electrode configured to be connected to the hetero semiconductor region; and 5) a drain electrode configured to be connected to the semiconductor base.
摘要翻译：一种半导体器件，包括：1）具有第一面的半导体基底; 2）异质半导体区域，被配置为在带隙中接触半导体基底的第一面并且不同于半导体基底，半导体基底和异质半导体区域在其间限定异质半导体区域中的接合部分，杂质浓度引入至少包括所述接合部分的第一特定区域小于或等于包含在所述异质半导体区域中的半导体材料的固溶极限; 3）通过栅极绝缘膜在与所述接合部分相邻的特定位置处形成的栅电极; 4）构造成连接到所述异质半导体区域的源电极; 以及5）被配置为连接到所述半导体基底的漏电极。

32. 发明申请

US20070221955A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070221955A1
公开(公告)日：2007-09-27
申请号：US11724389
申请日：2007-03-15
申请人： Yoshio Shimoida , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami , Masakatsu Hoshi
发明人： Yoshio Shimoida , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami , Masakatsu Hoshi
IPC分类号： H01L29/739
CPC分类号： H01L29/7828 , H01L21/0273 , H01L21/32139 , H01L29/1608 , H01L29/267 , H01L29/4236 , H01L29/66068
摘要： A trench is formed extending from a surface of a hetero semiconductor region of a polycrystal silicon to the drain region. Further, a driving point of the field effect transistor, where a gate insulating film, the hetero semiconductor region and the drain region are adjoined, is formed at a position spaced apart from a side wall of the trench.
摘要翻译：形成从多晶硅的异质半导体区域的表面延伸到漏极区域的沟槽。此外，栅极绝缘膜，异质半导体区域和漏极区域相邻的场效应晶体管的驱动点形成在与沟槽的侧壁间隔开的位置处。

33. 发明申请

US20070181886A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070181886A1
公开(公告)日：2007-08-09
申请号：US11701429
申请日：2007-02-02
申请人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
发明人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L31/0312
CPC分类号： H01L29/267 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device, includes: a first conductivity-semiconductor substrate; a hetero semiconductor region for forming a hetero junction with the first conductivity-semiconductor substrate; a gate electrode adjacent to a part of the hetero junction by way of a gate insulating film; a drain electrode connecting to the first conductivity-semiconductor substrate; a source electrode connecting to the hetero semiconductor region; and a second conductivity-semiconductor region formed on a part of a first face of the first conductivity-semiconductor substrate in such a configuration as to oppose the gate electrode via the gate insulating film, the gate insulating film, the hetero semiconductor region and the first conductivity-semiconductor substrate contacting each other to thereby form a triple contact point. A first face of the second conductivity-semiconductor region has such an impurity concentration that allows a field from the gate electrode to form an inversion layer on the first face of the second conductivity-semiconductor region.
摘要翻译：一种半导体器件，包括：第一导电半导体衬底; 用于与第一导电半导体衬底形成异质结的异质半导体区域; 通过栅绝缘膜与所述异质结的一部分相邻的栅电极; 连接到所述第一导电半导体衬底的漏电极; 连接到所述异质半导体区域的源电极; 以及第二导电半导体区域，形成在第一导电半导体基板的第一面的一部分上，以与栅电极相对的方式经由栅极绝缘膜，栅极绝缘膜，异质半导体区域和第一导电半导体区域导电性半导体基板彼此接触，从而形成三重接触点。第二导电率半导体区域的第一面具有允许来自栅电极的场在第二导电半导体区域的第一面上形成反型层的杂质浓度。

34. 发明授权

US07531396B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07531396B2
公开(公告)日：2009-05-12
申请号：US11374418
申请日：2006-03-14
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
IPC分类号： H01L21/338 , H01L21/066
CPC分类号： H01L29/66068 , H01L21/8213 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/1608 , H01L29/267 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/7828
摘要： A method of manufacturing a semiconductor device is disclosed. The semiconductor device includes a semiconductor body of a first conductivity type, a hetero semiconductor region adjacent to one main surface of the semiconductor body and having a band gap different from that of the semiconductor body, and a gate electrode formed in a junction portion between the hetero semiconductor region and the semiconductor body through a gate insulating film. The method includes a first process of forming a predetermined trench by using a mask layer having a predetermined opening on one main surface side of the semiconductor body, a second process of forming a buried region adjacent to at least a side wall of the trench and so as to extend from the trench, a third process of forming a hetero semiconductor layer so as to adjoin the semiconductor body and the buried region, and a fourth process of forming the hetero semiconductor region by patterning the hetero semiconductor layer.
摘要翻译：公开了制造半导体器件的方法。半导体器件包括第一导电类型的半导体本体，与半导体本体的一个主表面相邻且具有与半导体本体不同的带隙的异质半导体区域，以及形成在该半导体器件之间的接合部分中的栅电极异质半导体区域和半导体本体通过栅极绝缘膜。该方法包括通过使用在半导体主体的一个主表面侧上具有预定开口的掩模层来形成预定沟槽的第一工艺，形成与沟槽的至少侧壁相邻的掩埋区域的第二工艺从沟槽延伸，形成与半导体本体和掩埋区相邻的异质半导体层的第三工序，以及通过图案化杂半导体层形成异质半导体区的第四工序。

35. 发明授权

US07183575B2 High reverse voltage silicon carbide diode and method of manufacturing the same high reverse voltage silicon carbide diode 有权
标题翻译：高反向电压碳化硅二极管和制造相同高反向碳化硅二极管的方法
公开(公告)号：US07183575B2
公开(公告)日：2007-02-27
申请号：US10368016
申请日：2003-02-19
申请人： Yoshio Shimoida , Saichirou Kaneko , Hideaki Tanaka , Masakatsu Hoshi , Kraisom Throngnumchai , Teruyoshi Mihara , Tetsuya Hayashi
发明人： Yoshio Shimoida , Saichirou Kaneko , Hideaki Tanaka , Masakatsu Hoshi , Kraisom Throngnumchai , Teruyoshi Mihara , Tetsuya Hayashi
IPC分类号： H01L29/15
CPC分类号： H01L29/267 , H01L29/1608 , H01L29/861
摘要： A high reverse voltage diode includes a hetero junction made up from a silicon carbide base layer, which constitutes a first semiconductor base layer, and a polycrystalline silicon layer, which constitutes a second semiconductor layer, and whose band gap is different from that of the silicon carbide base layer. A low concentration N type polycrystalline silicon layer is deposited on a first main surface side of the silicon carbide base layer, and a metal electrode is formed on a second main surface side of the silicon carbide base layer which is opposite to the first main surface side thereof.
摘要翻译：高反向电压二极管包括由构成第一半导体基底层的碳化硅基底层和构成第二半导体层的多晶硅层构成的异质结，并且其带隙与硅的带隙不同碳化物基层。在碳化硅基底层的第一主表面侧沉积低浓度N型多晶硅层，在与第一主表面侧相反的碳化硅基底层的第二主表面侧上形成金属电极其中。

36. 发明授权

US07476590B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07476590B2
公开(公告)日：2009-01-13
申请号：US11231799
申请日：2005-09-22
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
IPC分类号： H01L21/336
CPC分类号： H01L29/7828 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7827
摘要： A method of manufacturing a semiconductor device having: forming a hetero semiconductor layer on at least the major surface of the semiconductor substrate body of a first conductivity type; etching the hetero semiconductor layer selectively by use of a mask layer having openings in way that the hetero semiconductor layer remains to be not etched with a predetermined thickness; oxidizing an exposed parts of the hetero semiconductor layer; forming the hetero semiconductor region by etching a oxidized film formed in the oxidizing; and forming the gate insulating film in a way that the gate insulating film makes an intimate contact with the hetero semiconductor region and the semiconductor substrate body. The bandgap of the hetero semiconductor layer is different from that of the semiconductor substrate body. The gate electrode is arranged in a junction part between the hetero semiconductor region and the semiconductor substrate body with the gate insulating film interposed between the gate electrode and the junction part.
摘要翻译：一种制造半导体器件的方法，其特征在于：在至少在第一导电类型的半导体衬底主体的主表面上形成杂半导体层; 通过使用具有开口的掩模层选择性地蚀刻异质半导体层，使得异质半导体层保持不被预定厚度蚀刻; 氧化杂半导体层的暴露部分; 通过蚀刻氧化膜形成的氧化膜来形成异质半导体区域; 以及栅极绝缘膜与异质半导体区域和半导体衬底本体紧密接触的方式形成栅极绝缘膜。异质半导体层的带隙与半导体衬底本体的带隙不同。栅电极配置在异质半导体区域和半导体衬底本体之间的接合部分中，栅极绝缘膜介于栅电极和接合部分之间。

37. 发明申请

US20060068537A1 Method of manufacturing semiconductor device 有权
公开(公告)号：US20060068537A1
公开(公告)日：2006-03-30
申请号：US11231799
申请日：2005-09-22
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7828 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7827
摘要： A method of manufacturing a semiconductor device having: forming a hetero semiconductor layer on at least the major surface of the semiconductor substrate body of a first conductivity type; etching the hetero semiconductor layer selectively by use of a mask layer having openings in way that the hetero semiconductor layer remains to be not etched with a predetermined thickness; oxidizing an exposed parts of the hetero semiconductor layer; forming the hetero semiconductor region by etching a oxidized film formed in the oxidizing; and forming the gate insulating film in a way that the gate insulating film makes an intimate contact with the hetero semiconductor region and the semiconductor substrate body. The bandgap of the hetero semiconductor layer is different from that of the semiconductor substrate body. The gate electrode is arranged in a junction part between the hetero semiconductor region and the semiconductor substrate body with the gate insulating film interposed between the gate electrode and the junction part.

38. 发明授权

US07521731B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07521731B2
公开(公告)日：2009-04-21
申请号：US11444433
申请日：2006-06-01
申请人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka
发明人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka
IPC分类号： H01L31/0328
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1608 , H01L29/2003 , H01L29/66068 , H01L29/66712 , H01L29/66734 , H01L29/7813 , H01L29/8083
摘要： A semiconductor device of the invention includes a first conductive type semiconductor base substrate; and a switching mechanism which is formed on a first main surface of the semiconductor base substrate and switches ON/OFF of a current. In the semiconductor base substrate, a plurality of columnar hetero-semiconductor regions are formed at spaced intervals within the semiconductor substrate, and the hetero-semiconductor regions are made of a semiconductor material having a different band gap from the semiconductor substrate and extend between the first main surface and a second main surface opposite to the first main surface.
摘要翻译：本发明的半导体器件包括：第一导电型半导体基底; 以及切换机构，其形成在所述半导体基板的第一主面上并切换电流的开/关。在半导体基板中，多个柱状异质半导体区域在半导体衬底内隔开间隔地形成，并且异质半导体区域由与半导体衬底具有不同带隙的半导体材料制成，并且在第一主表面和与第一主表面相对的第二主表面。

39. 发明申请

US20070298586A1 Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20070298586A1
公开(公告)日：2007-12-27
申请号：US11454818
申请日：2006-06-21
申请人： Hideaki Tanaka , Masakatsu Hoshi , Yoshio Shimoida , Tetsuya Hayashi
发明人： Hideaki Tanaka , Masakatsu Hoshi , Yoshio Shimoida , Tetsuya Hayashi
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L29/66068 , H01L21/6835 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/267 , H01L29/6606 , H01L29/7828 , H01L29/861 , H01L2221/68363
摘要： The present invention provides a method of manufacturing a semiconductor device. The semiconductor device comprises a semiconductor base made of a first semiconductor material; and a hetero-semiconductor region made of a second semiconductor material having a different band gap from the first semiconductor material and forming a heterojunction with the semiconductor base. The formation of the heterojunction is accomplished by bonding together the semiconductor base and a substrate made of the second semiconductor material.
摘要翻译：本发明提供一种制造半导体器件的方法。半导体器件包括由第一半导体材料制成的半导体基底; 以及由与第一半导体材料具有不同带隙并与半导体基底形成异质结的第二半导体材料制成的异质半导体区域。异质结的形成通过将半导体基底和由第二半导体材料制成的基底结合在一起来实现。

40. 发明申请

US20070218596A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070218596A1
公开(公告)日：2007-09-20
申请号：US11374418
申请日：2006-03-14
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L29/66068 , H01L21/8213 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/1608 , H01L29/267 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/7828
摘要： A method of manufacturing a semiconductor device is disclosed. The semiconductor device includes a semiconductor body of a first conductivity type, a hetero semiconductor region adjacent to one main surface of the semiconductor body and having a band gap different from that of the semiconductor body, and a gate electrode formed in a junction portion between the hetero semiconductor region and the semiconductor body through a gate insulating film. The method includes a first process of forming a predetermined trench by using a mask layer having a predetermined opening on one main surface side of the semiconductor body, a second process of forming a buried region adjacent to at least a side wall of the trench and so as to extend from the trench, a third process of forming a hetero semiconductor layer so as to adjoin the semiconductor body and the buried region, and a fourth process of forming the hetero semiconductor region by patterning the hetero semiconductor layer.
摘要翻译：公开了制造半导体器件的方法。半导体器件包括第一导电类型的半导体本体，与半导体本体的一个主表面相邻且具有与半导体本体不同的带隙的异质半导体区域，以及形成在该半导体器件之间的接合部分中的栅电极异质半导体区域和半导体本体通过栅极绝缘膜。该方法包括通过使用在半导体主体的一个主表面侧上具有预定开口的掩模层来形成预定沟槽的第一工艺，形成与沟槽的至少侧壁相邻的掩埋区域的第二工艺从沟槽延伸，形成与半导体本体和掩埋区相邻的异质半导体层的第三工序，以及通过图案化杂半导体层形成异质半导体区的第四工序。

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