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1. 发明授权

US07781786B2 Semiconductor device having a heterojunction diode and manufacturing method thereof 有权
标题翻译：具有异质结二极管的半导体器件及其制造方法
公开(公告)号：US07781786B2
公开(公告)日：2010-08-24
申请号：US11783577
申请日：2007-04-10
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L29/22 , H01L33/00 , H01L29/732 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L29/739 , H01L29/861 , H01L31/107 , H01L29/864
CPC分类号： H01L29/7808 , H01L29/0619 , H01L29/1608 , H01L29/165 , H01L29/6606 , H01L29/7802 , H01L29/7811 , H01L29/7828 , H01L29/8083 , H01L29/861 , H01L29/8618 , H01L29/872
摘要： Impurity concentration of a second semiconductor region is set such that when a predetermined reverse bias is applied to a heterojunction diode configured by a first semiconductor region and the second semiconductor region, a breakdown voltage at least in a heterojunction region other than outer peripheral ends of the heterojunction diode is a breakdown voltage of a semiconductor device.
摘要翻译：设定第二半导体区域的杂质浓度，使得当将预定的反向偏压施加到由第一半导体区域和第二半导体区域构成的异质结二极管时，至少在异种结区以外的击穿电压异质结二极管是半导体器件的击穿电压。

2. 发明申请

US20090233408A1 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20090233408A1
公开(公告)日：2009-09-17
申请号：US11988944
申请日：2006-06-26
申请人： Shigeharu Yamagami , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Yoshio Shimoida
发明人： Shigeharu Yamagami , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Yoshio Shimoida
IPC分类号： H01L21/336 , H01L21/22
CPC分类号： H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7827
摘要： A method of manufacturing a semiconductor device having a polycrystalline silicon layer (5) includes; a step of forming a mask layer (7) on the polycrystalline silicon layer (5); a step of forming a side wall (8) that is provided on a side face of the mask layer (7) and covers part of the polycrystalline silicon layer (6); a step of doping an impurity (52) into the polycrystalline silicon layer (5) by using at least one of the mask layer (7) and the side wall (8) as a mask; and a step of etching the polycrystalline silicon layer (5, 6) by using at least one of the mask layer (7) and the side wall (8) as a mask.
摘要翻译：一种制造具有多晶硅层（5）的半导体器件的方法包括：在多晶硅层（5）上形成掩模层（7）的步骤; 形成设置在掩模层（7）的侧面并覆盖多晶硅层（6）的一部分的侧壁（8）的步骤; 通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模将杂质（52）掺杂到多晶硅层（5）中的步骤; 以及通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模来蚀刻多晶硅层（5,6）的步骤。

3. 发明授权

US07476590B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07476590B2
公开(公告)日：2009-01-13
申请号：US11231799
申请日：2005-09-22
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
IPC分类号： H01L21/336
CPC分类号： H01L29/7828 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7827
摘要： A method of manufacturing a semiconductor device having: forming a hetero semiconductor layer on at least the major surface of the semiconductor substrate body of a first conductivity type; etching the hetero semiconductor layer selectively by use of a mask layer having openings in way that the hetero semiconductor layer remains to be not etched with a predetermined thickness; oxidizing an exposed parts of the hetero semiconductor layer; forming the hetero semiconductor region by etching a oxidized film formed in the oxidizing; and forming the gate insulating film in a way that the gate insulating film makes an intimate contact with the hetero semiconductor region and the semiconductor substrate body. The bandgap of the hetero semiconductor layer is different from that of the semiconductor substrate body. The gate electrode is arranged in a junction part between the hetero semiconductor region and the semiconductor substrate body with the gate insulating film interposed between the gate electrode and the junction part.
摘要翻译：一种制造半导体器件的方法，其特征在于：在至少在第一导电类型的半导体衬底主体的主表面上形成杂半导体层; 通过使用具有开口的掩模层选择性地蚀刻异质半导体层，使得异质半导体层保持不被预定厚度蚀刻; 氧化杂半导体层的暴露部分; 通过蚀刻氧化膜形成的氧化膜来形成异质半导体区域; 以及栅极绝缘膜与异质半导体区域和半导体衬底本体紧密接触的方式形成栅极绝缘膜。异质半导体层的带隙与半导体衬底本体的带隙不同。栅电极配置在异质半导体区域和半导体衬底本体之间的接合部分中，栅极绝缘膜介于栅电极和接合部分之间。

4. 发明申请

US20080023707A1 Semiconductor device and method of producing the semiconductor device 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080023707A1
公开(公告)日：2008-01-31
申请号：US11493604
申请日：2006-07-27
申请人： Hideaki Tanaka , Masakatsu Hoshi , Yoshio Shimoida , Tetsuya Hayashi , Shigeharu Yamagami
发明人： Hideaki Tanaka , Masakatsu Hoshi , Yoshio Shimoida , Tetsuya Hayashi , Shigeharu Yamagami
IPC分类号： H01L31/0312 , H01L21/00
CPC分类号： H01L29/66068 , H01L29/0615 , H01L29/1608 , H01L29/267 , H01L29/6606 , H01L29/7827 , H01L29/861
摘要： A semiconductor device, includes: 1) an electric field relaxing area, including: i) a hetero junction formed by the followings: a) a first semiconductor material, and b) a second semiconductor material different from the first semiconductor material in band gap, and ii) an impurity introducing area so formed on the first semiconductor material as to contact the hetero junction.
摘要翻译：一种半导体器件，包括：1）电场缓和区域，包括：i）通过以下方式形成的异质结：a）第一半导体材料，以及b）与带隙中的第一半导体材料不同的第二半导体材料，以及ii）如此形成在第一半导体材料上以与异质结接触的杂质引入区域。

5. 发明申请

US20070252174A1 Method of manufacturing semiconductor device and semiconductor device 审中-公开
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US20070252174A1
公开(公告)日：2007-11-01
申请号：US11790380
申请日：2007-04-25
申请人： Shigeharu Yamagami , Masakatsu Hoshi , Yoshio Shimoida , Tetsuya Hayashi , Hideaki Tanaka
发明人： Shigeharu Yamagami , Masakatsu Hoshi , Yoshio Shimoida , Tetsuya Hayashi , Hideaki Tanaka
IPC分类号： H01L31/00
CPC分类号： H01L29/66068 , H01L21/046 , H01L29/42376 , H01L29/7827
摘要： After a polycrystalline silicon as a hetero-semiconductor region forming a heterojunction with a semiconductor base is formed on an epitaxial layer configuring the semiconductor base, the unevenness on the surface of the polycrystalline silicon is planarized before a gate insulating film is formed. Alternatively, as the hetero-semiconductor region, amorphous or microcrystal hetero-semiconductor of which crystal grain diameter is small is used. When an amorphous or microcrystal hetero-semiconductor is deposited as the hetero-semiconductor region, a recrystallization annealing process of transforming into the polycrystalline silicon can be applied after the deposition. As a material of the semiconductor base, silicon carbide, gallium nitride or diamond can be used. As a material of the hetero-semiconductor region, silicon, silicon germanium, germanium, or gallium arsenide can be used.
摘要翻译：在构成半导体基底的外延层上形成多晶硅作为形成与半导体基底的异质结的异质半导体区域之后，在形成栅极绝缘膜之前，将多晶硅的表面上的不平坦度平坦化。或者，作为异质半导体区域，使用结晶粒径小的非晶或微晶异质半导体。当非晶或微晶异质半导体作为异质半导体区域沉积时，可以在沉积之后施加转化为多晶硅的再结晶退火工艺。作为半导体基底的材料，可以使用碳化硅，氮化镓或金刚石。作为异质半导体区域的材料，可以使用硅，硅锗，锗或砷化镓。

6. 发明申请

US20060118818A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060118818A1
公开(公告)日：2006-06-08
申请号：US11289460
申请日：2005-11-30
申请人： Yoshio Shimoida , Masakatsu Hoshi , Hideaki Tanaka , Tetsuya Hayashi , Toshiro Shinohara , Shigeharu Yamagami
发明人： Yoshio Shimoida , Masakatsu Hoshi , Hideaki Tanaka , Tetsuya Hayashi , Toshiro Shinohara , Shigeharu Yamagami
IPC分类号： H01L29/732
CPC分类号： H01L29/7398 , H01L29/0834 , H01L29/1608 , H01L29/267 , H01L29/7391 , H01L29/7392 , H01L29/7395 , H01L29/7397
摘要： An aspect of the present invention provides a semiconductor device that includes, a first semiconductor body of a first conductivity type, a first switching mechanism provided on the first semiconductor body, configured and arranged to switch on/off current flowing through the semiconductor device, and a first reverse-blocking heterojunction diode provided on the semiconductor body, configured and arranged to block current reverse to the current switched on/off by the first switching mechanism.
摘要翻译：本发明的一个方面提供一种半导体器件，其包括：第一导电类型的第一半导体本体，设置在第一半导体本体上的第一开关机构，被配置和布置成用于接通流过半导体器件的导通/截止电流;以及设置在所述半导体本体上的第一反向阻挡异质结二极管，被配置和布置成阻止与所述第一开关机构相反的电流接通/断开。

7. 发明申请

US20060068537A1 Method of manufacturing semiconductor device 有权
公开(公告)号：US20060068537A1
公开(公告)日：2006-03-30
申请号：US11231799
申请日：2005-09-22
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7828 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7827
摘要： A method of manufacturing a semiconductor device having: forming a hetero semiconductor layer on at least the major surface of the semiconductor substrate body of a first conductivity type; etching the hetero semiconductor layer selectively by use of a mask layer having openings in way that the hetero semiconductor layer remains to be not etched with a predetermined thickness; oxidizing an exposed parts of the hetero semiconductor layer; forming the hetero semiconductor region by etching a oxidized film formed in the oxidizing; and forming the gate insulating film in a way that the gate insulating film makes an intimate contact with the hetero semiconductor region and the semiconductor substrate body. The bandgap of the hetero semiconductor layer is different from that of the semiconductor substrate body. The gate electrode is arranged in a junction part between the hetero semiconductor region and the semiconductor substrate body with the gate insulating film interposed between the gate electrode and the junction part.

8. 发明授权

US08441036B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08441036B2
公开(公告)日：2013-05-14
申请号：US11724389
申请日：2007-03-15
申请人： Yoshio Shimoida , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami , Masakatsu Hoshi
发明人： Yoshio Shimoida , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami , Masakatsu Hoshi
IPC分类号： H01L29/739
CPC分类号： H01L29/7828 , H01L21/0273 , H01L21/32139 , H01L29/1608 , H01L29/267 , H01L29/4236 , H01L29/66068
摘要： A trench is formed extending from a surface of a hetero semiconductor region of a polycrystal silicon to the drain region. Further, a driving point of the field effect transistor, where a gate insulating film, the hetero semiconductor region and the drain region are adjoined, is formed at a position spaced apart from a side wall of the trench.
摘要翻译：形成从多晶硅的异质半导体区域的表面延伸到漏极区域的沟槽。此外，栅极绝缘膜，异质半导体区域和漏极区域相邻的场效应晶体管的驱动点形成在与沟槽的侧壁间隔开的位置处。

9. 发明授权

US08164116B2 Semiconductor device with hetero semiconductor region and method of manufacturing the same 有权
标题翻译：具有异质半导体区域的半导体器件及其制造方法
公开(公告)号：US08164116B2
公开(公告)日：2012-04-24
申请号：US12065847
申请日：2006-08-22
申请人： Tetsuya Hayashi , Yoshio Shimoida , Masakatsu Hoshi , Hideaki Tanaka , Shigeharu Yamagami
发明人： Tetsuya Hayashi , Yoshio Shimoida , Masakatsu Hoshi , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L29/66
CPC分类号： H01L29/861 , H01L21/046 , H01L29/0623 , H01L29/0653 , H01L29/1608 , H01L29/267 , H01L29/6606 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device includes: a semiconductor base; a hetero semiconductor region which is in contact with the semiconductor base and which has a band gap different from that of the semiconductor base; a first electrode connected to the hetero semiconductor region; and a second electrode forming an ohmic contact to the semiconductor base. The hetero semiconductor region includes a laminated hetero semiconductor region formed by laminating a plurality of semiconductor layers in which crystal alignment is discontinuous at a boundary between at least two layers.
摘要翻译：半导体器件包括：半导体基底; 与半导体基底接触并且具有与半导体基底不同的带隙的异质半导体区域; 连接到所述异质半导体区域的第一电极; 以及形成与半导体基底的欧姆接触的第二电极。异质半导体区域包括通过层叠在至少两层之间的边界处晶体取向不连续的多个半导体层而形成的层叠异质半导体区域。

10. 发明申请

US20110117699A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110117699A1
公开(公告)日：2011-05-19
申请号：US13014190
申请日：2011-01-26
申请人： Tetsuya HAYASHI , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
发明人： Tetsuya HAYASHI , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L21/336 , H01L21/04
CPC分类号： H01L29/7828 , H01L29/0623 , H01L29/1608 , H01L29/267 , H01L29/66068
摘要： A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.
摘要翻译：制备由半导体材料制成的半导体衬底，并且在半导体衬底上形成异质半导体区域，以在异质半导体区域和半导体衬底之间的界面中形成异质结。异质半导体区域由具有与半导体材料的带隙不同的带隙的半导体材料制成，并且异质半导体区域的一部分包括膜厚度比其他部分薄的膜厚控制部分。通过以等于膜厚控制部分的膜厚的厚度氧化杂半导体区域，形成与异质结相邻的栅极绝缘膜。在栅极绝缘膜上形成栅电极。这使得可以制造包括具有较低导通电阻的栅极绝缘膜以及更高的绝缘特性和可靠性的半导体器件。

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