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31. 发明授权

US07372299B2 Differential clock tree in an integrated circuit 有权
标题翻译：差分时钟树在集成电路中
公开(公告)号：US07372299B2
公开(公告)日：2008-05-13
申请号：US11511779
申请日：2006-08-29
申请人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
发明人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
IPC分类号： H03K19/177
CPC分类号： G06F1/10 , H03K5/2481
摘要： A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.
摘要翻译：一种时钟分配网络，具有：主干线，被配置为提供差分时钟信号; 耦合到所述主干线的多个分支，用于将所述差分时钟信号分配给所述集成电路上的多个电路元件; 以及将主干线连接到多个分支的多个开关。

32. 发明授权

US07129765B2 Differential clock tree in an integrated circuit 有权
公开(公告)号：US07129765B2
公开(公告)日：2006-10-31
申请号：US10836722
申请日：2004-04-30
申请人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
发明人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10 , H03K5/2481
摘要： A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

33. 发明授权

US07126406B2 Programmable logic device having an embedded differential clock tree 有权
标题翻译：具有嵌入式差分时钟树的可编程逻辑器件
公开(公告)号：US07126406B2
公开(公告)日：2006-10-24
申请号：US10837009
申请日：2004-04-30
申请人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
发明人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/1774 , H03K19/17784 , H03K19/17796
摘要： A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.
摘要翻译：一种时钟分配网络，具有：骨干时钟信号线，被配置为提供差分时钟信号; 多个分支耦合到主干时钟信号线，用于将差分时钟信号分配给多个可编程功能元件; 耦合到第一分支的第一叶节点，其中所述第一叶节点被配置为将所述差分时钟信号提供给第一可编程功能元件; 以及耦合到第二分支的第二叶节点，其中所述第二叶节点被配置为将从所述差分时钟信号导出的单端时钟信号提供给第二可编程功能元件。

34. 发明授权

US07111220B1 Network physical layer with embedded multi-standard CRC generator 有权
标题翻译：具有嵌入式多标准CRC发生器的网络物理层
公开(公告)号：US07111220B1
公开(公告)日：2006-09-19
申请号：US10090519
申请日：2002-03-01
申请人： Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Hare K. Verma , Philip M. Freidin
发明人： Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Hare K. Verma , Philip M. Freidin
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6519 , H04L69/32 , H04L69/324
摘要： Disclosed are methods and structures for preparing data for transmission over a network. In an embodiment consistent with the OSI network model, transmit and receive CRC generators are moved from the link layer to the physical layer, which frees up valuable programmable logic resources when a programmable logic device is employed to perform the functions of the link layer. The CRC generators of the physical layer comply with a plurality of network communication standards.
摘要翻译：公开了用于准备通过网络传输的数据的方法和结构。在与OSI网络模型一致的实施例中，发送和接收CRC发生器从链路层移动到物理层，当使用可编程逻辑器件来执行链路层的功能时，发送和接收CRC发生器释放有价值的可编程逻辑资源。物理层的CRC生成器符合多个网络通信标准。

35. 发明授权

US06960933B1 Variable data width operation in multi-gigabit transceivers on a programmable logic device 有权
标题翻译：可编程逻辑器件上的千兆位收发器中的可变数据宽度操作
公开(公告)号：US06960933B1
公开(公告)日：2005-11-01
申请号：US10618146
申请日：2003-07-11
申请人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
发明人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
IPC分类号： H03K19/177 , H04L25/45
CPC分类号： H03K19/1774 , H03K19/17744 , H04L25/45
摘要： A transmit variable-width interface can be programmed to convert an electronic digital data path that is either 1N, 2N, 4N, or 8N bits wide into a data path that is 2N bits wide, either by serializing bits (4N- or 8N-bit cases), re-clocking bits (2N-bit case), or grouping bits (1N-bit case). A receive variable-width interface can be programmed to convert a data path 2N bits wide into a data path that is 1N, 2N, 4N, or 8N bits wide. The widths of the two variable-width data paths are controlled independently. The variable-width interfaces are coupled between a multi-gigabit transceiver and core logic of a programmable logic device. The incoming and outgoing data paths of the variable-width interfaces have separate clocks signals that are synchronized such that small amounts of skew in these clock signals do not disrupt the operation of the variable-width interfaces.
摘要翻译：传输可变宽度接口可编程为将1N，2N，4N或8N位宽的电子数字数据路径转换为2N位宽的数据通道，通过将位（4N或8N位）情况），重新计时位（2N位情况）或分组位（1N位情况）。接收可变宽度接口可以被编程为将2N位宽的数据路径转换成1N，2N，4N或8N位宽的数据路径。两个可变宽度数据路径的宽度被独立地控制。可变宽度接口耦合在可编程逻辑器件的千兆位收发器和核心逻辑之间。可变宽度接口的输入和输出数据路径具有同步的分离时钟信号，使得这些时钟信号中的少量偏移不会中断可变宽度接口的操作。

36. 发明授权

US06617877B1 Variable data width operation in multi-gigabit transceivers on a programmable logic device 有权
标题翻译：可编程逻辑器件上的千兆位收发器中的可变数据宽度操作
公开(公告)号：US06617877B1
公开(公告)日：2003-09-09
申请号：US10090286
申请日：2002-03-01
申请人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
发明人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
IPC分类号： H03K19177
CPC分类号： H03K19/1774 , H03K19/17744 , H04L25/45
摘要： A transmit variable-width interface can be programmed to convert an electronic digital data path that is either 1N, 2N, 4N, or 8N bits wide into a data path that is 2N bits wide, either by serializing bits (4N- or 8N-bit cases), re-clocking bits (2N-bit case), or grouping bits (1N-bit case). A receive variable-width interface can be programmed to convert a data path 2N bits wide into a data path that is 1N, 2N, 4N, or 8N bits wide. The widths of the two variable-width data paths are controlled independently. The variable-width interfaces are coupled between a multi-gigabit transceiver and core logic of a programmable logic device. The incoming and outgoing data paths of the variable-width interfaces have separate clocks signals that are synchronized such that small amounts of skew in these clock signals do not disrupt the operation of the variable-width interfaces.
摘要翻译：传输可变宽度接口可编程为将1N，2N，4N或8N位宽的电子数字数据路径转换为2N位宽的数据通道，通过将位（4N或8N位）情况），重新计时位（2N位情况）或分组位（1N位情况）。接收可变宽度接口可以被编程为将2N位宽的数据路径转换成1N，2N，4N或8N位宽的数据路径。两个可变宽度数据路径的宽度被独立地控制。可变宽度接口耦合在可编程逻辑器件的千兆位收发器和核心逻辑之间。可变宽度接口的输入和输出数据路径具有同步的分离时钟信号，使得这些时钟信号中的少量偏移不会中断可变宽度接口的操作。

37. 发明授权

US5497108A BICMOS repeater circuit for a programmable logic device 失效
标题翻译：用于可编程逻辑器件的BICMOS中继器电路
公开(公告)号：US5497108A
公开(公告)日：1996-03-05
申请号：US352402
申请日：1994-12-08
申请人： Suresh M. Menon , Stanley Wilson , Tsung C. Whang
发明人： Suresh M. Menon , Stanley Wilson , Tsung C. Whang
IPC分类号： H03K17/567 , H03K19/173 , H03K19/0175
CPC分类号： H03K17/567 , H03K19/1736
摘要： A programmable logic device includes a plurality of logic cells in which logic functions are performed, a plurality of input lines for supplying signals to be processed by the logic cells, a plurality of output lines for receiving signals that have been processed by the logic cells, and a plurality of repeater circuits combining bipolar and CMOS transistor technologies for transferring data from one point in the PLD to another point. Unidirectional repeater circuits transfer data from a first data bus in the PLD to a second data bus in the PLD. Bidirectional repeater circuits maintain signal integrity by transferring data along the length of a single PLD data bus. The bipolar technology in the repeater circuits provides superior speed in data transfer, while the CMOS technology limits power consumption of the repeater circuits.
摘要翻译：可编程逻辑器件包括执行逻辑功能的多个逻辑单元，用于提供由逻辑单元处理的信号的多条输入线，用于接收由逻辑单元处理的信号的多条输出线，以及组合用于将数据从PLD中的一个点传送到另一个点的双极和CMOS晶体管技术的多个中继器电路。单向中继器电路将数据从PLD中的第一数据总线传送到PLD中的第二数据总线。双向中继器电路通过沿单个PLD数据总线的长度传输数据来保持信号完整性。中继器电路中的双极技术在数据传输方面提供卓越的速度，而CMOS技术限制了中继器电路的功耗。

38. 发明授权

US4795918A Bandgap voltage reference circuit with an npn current bypass circuit 失效
标题翻译：带隙电压参考电路，带npn电流旁路电路
公开(公告)号：US4795918A
公开(公告)日：1989-01-03
申请号：US045950
申请日：1987-05-01
申请人： Suresh M. Menon , Jay L. Cohan
发明人： Suresh M. Menon , Jay L. Cohan
IPC分类号： G05F3/30 , G05F3/20
CPC分类号： G05F3/30 , Y10S323/907
摘要： A temperature compensated bandgap voltage reference circuit employs an npn transistor based bypass circuit to maintain a constant collector current within the reference circuit. This bypass circuit draws a nominal current from the bandgap voltage reference circuit. The value of this current is set by a bias circuit responsive to changes in the supply voltage. As the supply voltage changes, the bias circuit varies the conductance of a bypass transistor to draw more or less current and thereby maintain the collector current within the reference circuit constant.

39. 发明授权

US07353487B1 Regional signal-distribution network for an integrated circuit 有权
标题翻译：集成电路的区域信号分配网络
公开(公告)号：US07353487B1
公开(公告)日：2008-04-01
申请号：US10981877
申请日：2004-11-05
申请人： Jason R. Bergendahl , Ping-Chen Liu , Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Steven P. Young , Trevor J. Bauer
发明人： Jason R. Bergendahl , Ping-Chen Liu , Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Steven P. Young , Trevor J. Bauer
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/62
摘要： Signal distribution of a regional signal is described. A programmable logic device includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.
摘要翻译：描述区域信号的信号分布。可编程逻辑器件包括全局信号分配网络，区域信号分配网络和区域缓冲器。区域缓冲区具有耦合在区域信号分配网络末端的输出。区域信号分配网络通过互连瓦片耦合到可配置的逻辑块。区域缓冲器耦合到具有区域时钟的输入/输出块。另外描述了用于区域信号分配的源同步接口。

40. 发明授权

US07317773B2 Double data rate flip-flop 有权
标题翻译：双倍数据率触发器
公开(公告)号：US07317773B2
公开(公告)日：2008-01-08
申请号：US10888203
申请日：2004-07-09
申请人： Steven P. Young , Suresh M. Menon , Ketan Sodha , Richard A. Carberry , Joseph H. Hassoun
发明人： Steven P. Young , Suresh M. Menon , Ketan Sodha , Richard A. Carberry , Joseph H. Hassoun
IPC分类号： H04L7/00
CPC分类号： H04J3/047
摘要： Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.
摘要翻译：用于使逻辑路径上的数据传输的吞吐率加倍的方法和装置包括提供交替地接收待发送的数据流的连续位的两个锁存器和具有由两个分离的时钟交替计时的数据传输路径的多路复用器基本相差180度。

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