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1. 发明授权

US07187709B1 High speed configurable transceiver architecture 有权
标题翻译：高速可配置收发器架构
公开(公告)号：US07187709B1
公开(公告)日：2007-03-06
申请号：US10090250
申请日：2002-03-01
申请人： Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Paul T. Sasaki , Philip M. Freidin , Santiago G. Asuncion , Philip D. Costello , Vasisht M. Vadi , Adebabay M. Bekele , Hare K. Verma
发明人： Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Paul T. Sasaki , Philip M. Freidin , Santiago G. Asuncion , Philip D. Costello , Vasisht M. Vadi , Adebabay M. Bekele , Hare K. Verma
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： G06F15/7867
摘要： One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.
摘要翻译：一个或多个可配置的收发器可以在集成电路上制造。收发器包含各种组件，具有可通过打开或关闭配置存储单元来配置的选项。该集成电路还可以包含可编程织物。收发器中的其他组件可以具有由可编程结构控制的选项。集成电路还可以包含一个或多个处理器核。处理器核心和收发器可以通过通过可编程结构的多个信号路径连接。

2. 发明授权

US07111220B1 Network physical layer with embedded multi-standard CRC generator 有权
标题翻译：具有嵌入式多标准CRC发生器的网络物理层
公开(公告)号：US07111220B1
公开(公告)日：2006-09-19
申请号：US10090519
申请日：2002-03-01
申请人： Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Hare K. Verma , Philip M. Freidin
发明人： Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Hare K. Verma , Philip M. Freidin
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6519 , H04L69/32 , H04L69/324
摘要： Disclosed are methods and structures for preparing data for transmission over a network. In an embodiment consistent with the OSI network model, transmit and receive CRC generators are moved from the link layer to the physical layer, which frees up valuable programmable logic resources when a programmable logic device is employed to perform the functions of the link layer. The CRC generators of the physical layer comply with a plurality of network communication standards.
摘要翻译：公开了用于准备通过网络传输的数据的方法和结构。在与OSI网络模型一致的实施例中，发送和接收CRC发生器从链路层移动到物理层，当使用可编程逻辑器件来执行链路层的功能时，发送和接收CRC发生器释放有价值的可编程逻辑资源。物理层的CRC生成器符合多个网络通信标准。

3. 发明授权

US08185237B2 Dispense verification meters 有权
标题翻译：分配验证表
公开(公告)号：US08185237B2
公开(公告)日：2012-05-22
申请号：US11966228
申请日：2007-12-28
申请人： Philip M. Freidin
发明人： Philip M. Freidin
IPC分类号： G06F17/00
CPC分类号： G01F25/0084 , G01F9/008 , G01F13/006
摘要： A dispense verification meter for measuring and verifying dispense operations (e.g., actual dispensed volumes) of media dispense systems. The dispense verification meter preferably automatically corrects zero offset drift, preferably samples the flow rate of media being dispensed at a sufficiently high sample rate, and verifies whether the desired dispense operation has been achieved.
摘要翻译：用于测量和验证介质分配系统的分配操作（例如，实际分配的体积）的分配验证计量器。分配验证表优选自动校正零偏移漂移，优选以足够高的采样速率对被分配的介质的流速进行采样，并且验证是否已经实现了所需的分配操作。

4. 发明授权

US5726584A Virtual high density programmable integrated circuit having addressable shared memory cells 失效
标题翻译：具有可寻址共享存储单元的虚拟高密度可编程集成电路
公开(公告)号：US5726584A
公开(公告)日：1998-03-10
申请号：US619286
申请日：1996-03-18
申请人： Philip M. Freidin
发明人： Philip M. Freidin
IPC分类号： H03K19/177 , H03K19/173 , H03K7/38
CPC分类号： H03K19/17776 , H03K19/1776
摘要： A virtual high density architecture having shared memory cells for a programmable integrated circuit (IC) is provided. The architecture includes logic modules, a configuration memory unit (CMU), and a global interconnect memory (GIMU) unit. A logic cycle is divided into a number of time intervals. For each time interval, the CMU outputs information to configure the logic modules and the interconnect structure to realize an individual circuit stage of a circuit. Input and output data pertinent to this individual stage are retrieved from and stored in the GIMU based on addressing information generated from the CMU for each time interval. The CMU continuously reprograms the logic modules and interconnect structure for each time interval to realize different stages of the circuit while information used between stages is stored in the GIMU. The architecture reuses the IC's complement of logic and other functional elements continuously during a logic cycle to implement the circuit as a series of circuit stages over time using a relatively limited number of logic and other functional elements to implement each stage. The GIMU is coupled to address and data buses and the data bus is coupled to each logic module. The GIMU contains individually addressable memory cells that are shared between logic modules across different time intervals providing an extremely flexible signal path between logic modules. The GIMU has a separate read and write port for each logic module.
摘要翻译：提供了具有用于可编程集成电路（IC）的共享存储器单元的虚拟高密度架构。该架构包括逻辑模块，配置存储单元（CMU）和全局互连存储器（GIMU）单元。逻辑循环被分成多个时间间隔。对于每个时间间隔，CMU输出信息以配置逻辑模块和互连结构，以实现电路的单独电路级。基于每个时间间隔从CMU生成的寻址信息，从GIMU检索和存储与该单独阶段相关的输入和输出数据。 CMU在每个时间间隔内连续重新编程逻辑模块和互连结构，以实现电路的不同阶段，同时在GIMU之间存储各个阶段之间的信息。该架构在逻辑循环期间重复使用IC的逻辑补充和其他功能元件，以使用相对有限数量的逻辑和其他功能元件实现每个阶段，将电路实现为一系列电路阶段。 GIMU耦合到地址和数据总线，数据总线耦合到每个逻辑模块。 GIMU包含独立可寻址的存储单元，可在不同时间间隔内在逻辑模块之间共享，从而在逻辑模块之间提供极其灵活的信号路径。 GIMU为每个逻辑模块提供单独的读写端口。

5. 发明授权

US5566123A Synchronous dual port ram 失效
标题翻译：同步双端口RAM
公开(公告)号：US5566123A
公开(公告)日：1996-10-15
申请号：US386972
申请日：1995-02-10
申请人： Philip M. Freidin , Edmond Y. Cheung , Charles R. Erickson , Tsung-Lu Syu
发明人： Philip M. Freidin , Edmond Y. Cheung , Charles R. Erickson , Tsung-Lu Syu
IPC分类号： G11C11/41 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/16 , H03K19/173 , H03K19/177 , G11C7/00
CPC分类号： H03K19/1736 , G11C7/1072 , G11C7/22 , G11C8/00 , G11C8/16 , H03K19/17704
摘要： A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.
摘要翻译：双端口模式下的可配置逻辑块（CLB）使用一个地址将相同的信息写入第一个RAM和第二个RAM。提供给第二函数发生器的输入信号可以用于独立于写入操作而非甚至异步地读取，从而显着地增加使用两组RAM的应用速度。同步模式下的CLB锁存适当的地址和数据信号，并产生选通的写使能信号。选通信号是自定时的，即写入操作是完全自动的，从而确保写操作在一个时钟周期内发生。

6. 发明申请

US20120211518A1 Dispense Verification Meters 有权
标题翻译：分配验证表
公开(公告)号：US20120211518A1
公开(公告)日：2012-08-23
申请号：US13461638
申请日：2012-05-01
申请人： Philip M. Freidin
发明人： Philip M. Freidin
IPC分类号： B67D7/16
CPC分类号： G01F25/0084 , G01F9/008 , G01F13/006
摘要： A dispense verification meter for measuring and verifying dispense operations (e.g., actual dispensed volumes) of media dispense systems. The dispense verification meter preferably automatically corrects zero offset drift, preferably samples the flow rate of media being dispensed at a sufficiently high sample rate, and verifies whether the desired dispense operation has been achieved.
摘要翻译：用于测量和验证介质分配系统的分配操作（例如，实际分配的体积）的分配验证计量器。分配验证表优选自动校正零偏移漂移，优选以足够高的采样速率对被分配的介质的流速进行采样，并且验证是否已经实现了所需的分配操作。

7. 发明申请

US20090171502A1 Dispense Verification Meters 有权
标题翻译：分配验证表
公开(公告)号：US20090171502A1
公开(公告)日：2009-07-02
申请号：US11966228
申请日：2007-12-28
申请人： Philip M. Freidin
发明人： Philip M. Freidin
IPC分类号： G06F17/00 , B67D5/08 , G01F1/00
CPC分类号： G01F25/0084 , G01F9/008 , G01F13/006
摘要： A dispense verification meter for measuring and verifying dispense operations (e.g., actual dispensed volumes) of media dispense systems. The dispense verification meter preferably automatically corrects zero offset drift, preferably samples the flow rate of media being dispensed at a sufficiently high sample rate, and verifies whether the desired dispense operation has been achieved.
摘要翻译：用于测量和验证介质分配系统的分配操作（例如，实际分配的体积）的分配验证计量器。分配验证表优选自动校正零偏移漂移，优选以足够高的采样速率对被分配的介质的流速进行采样，并且验证是否已经实现了所需的分配操作。

8. 发明授权

US5995988A Configurable parallel and bit serial load apparatus 有权
标题翻译：可配置并行和位串行负载设备
公开(公告)号：US5995988A
公开(公告)日：1999-11-30
申请号：US131536
申请日：1998-08-10
申请人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
发明人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
IPC分类号： H03K19/173 , H03K19/177 , G06F1/04 , G06F7/38
CPC分类号： H03K19/17776 , H03K19/1736 , H03K19/17748
摘要： An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.
摘要翻译：一种用于将配置信息加载到可编程集成电路（例如，FPGA）中的装置，可配置为在同一架构内执行并行加载或位串行加载。配置信息在每个N个串行位的数据帧中呈现给FPGA。每个数据帧被分成具有每个Y位的离散串行部分（例如，数据帧包括N / Y部分）。在并行模式下，这些部分被加载到分段配置寄存器中，每个编程周期一个部分，使得Y位并行加载到分段配置寄存器中。在并行加载期间的每个编程时钟周期，数据帧部分的所有位同时加载到配置寄存器的段（每个段的第一位位置），使得每个段在每个编程周期接收一位。然后将配置寄存器的位向下移一个，并为下一个数据帧部分重复循环。在这种机制下，Y位被并行加载到配置寄存器中，以提高传输速率。新型配置寄存器的架构使得其可以以串行模式配置以接收N位数据帧的单个串行比特流，用于向下兼容。

9. 发明授权

US5961576A Configurable parallel and bit serial load apparatus 有权
公开(公告)号：US5961576A
公开(公告)日：1999-10-05
申请号：US176626
申请日：1998-10-22
申请人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
发明人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
IPC分类号： H03K19/173 , H03K19/177 , G06F1/04 , G06F7/38
CPC分类号： H03K19/17776 , H03K19/1736
摘要： An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.

10. 发明授权

US5661660A Method for providing multiple function symbols 失效
标题翻译：提供多个功能符号的方法
公开(公告)号：US5661660A
公开(公告)日：1997-08-26
申请号：US239675
申请日：1994-05-09
申请人： Philip M. Freidin
发明人： Philip M. Freidin
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Logic is represented in a schematic capture program as a generic symbol. The generic symbol represents a single underlying logic circuit, thereby decreasing library space. The generic symbol includes a configuration memory which is represented on the symbol by a plurality of pins. The generic symbol is configured by indicating the logic signals placed on the plurality of pins. In this manner, the generic symbol significantly increases the design choices available to the end user. Moreover, the generic symbol allows access to the underlying logic of the circuit via the selected bit pattern, thereby advantageously permitting the end user to perform functional simulation within the schematic environment. In one embodiment, a plug symbol is provided to schematically connect to the generic symbol. This plug symbol represents a predetermined pattern of bits, thereby significantly simplifying configuring the logic in the schematic capture program.
摘要翻译：逻辑在示意图捕获程序中表示为通用符号。通用符号表示单个底层逻辑电路，从而减少库空间。通用符号包括通过多个引脚在符号上表示的配置存储器。通用符号通过指示放置在多个引脚上的逻辑信号来配置。以这种方式，通用符号显着增加了最终用户可用的设计选择。此外，通用符号允许通过所选位模式访问电路的底层逻辑，从而有利地允许最终用户在原理图环境内执行功能仿真。在一个实施例中，提供插头符号来示意性地连接到通用符号。该插头符号表示预定的比特模式，从而显着简化了在原理图捕获程序中配置逻辑。

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