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31. 发明授权

US08841652B2 Self aligned carbide source/drain FET 有权
标题翻译：自对准碳化物源极/漏极FET
公开(公告)号：US08841652B2
公开(公告)日：2014-09-23
申请号：US12627120
申请日：2009-11-30
申请人： Cyril Cabral, Jr. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
发明人： Cyril Cabral, Jr. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
IPC分类号： H01L29/08 , H01L29/16 , H01L29/775 , B82Y10/00 , H01L51/10 , H01L51/00 , H01L51/05
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/16 , H01L29/1602 , H01L51/0048 , H01L51/0541 , H01L51/105
摘要： A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.
摘要翻译：场效应晶体管包括金属碳化物源部分，金属碳化物漏极部分，将金属碳化物源部分与金属碳化物部分分离的绝缘碳部分，形成在绝缘和碳部分上的纳米结构，并将金属碳化物源部分连接到金属碳化物排出部分和形成在绝缘碳部分的至少一部分和至少一部分纳米结构上的栅堆叠。

32. 发明授权

US08717136B2 Inductor with laminated yoke 有权
标题翻译：带有叠片轭的电感器
公开(公告)号：US08717136B2
公开(公告)日：2014-05-06
申请号：US13347571
申请日：2012-01-10
申请人： Robert E. Fontana, Jr. , William J. Gallagher , Philipp Herget , Eugene J. O'Sullivan , Lubomyr T. Romankiw , Naigang Wang , Bucknell C. Webb
发明人： Robert E. Fontana, Jr. , William J. Gallagher , Philipp Herget , Eugene J. O'Sullivan , Lubomyr T. Romankiw , Naigang Wang , Bucknell C. Webb
IPC分类号： H01F27/30 , H01F5/00 , H01F27/28 , H01F27/24
CPC分类号： H01F41/042 , H01F27/2804 , H01F41/046 , H01F2017/0066 , H01F2027/348
摘要： A thin film inductor having yokes, one or more of which is laminated, and one or more conductors passing between the yokes. The laminated yoke or yokes help reduce eddy currents and/or hysteresis losses.
摘要翻译：一种薄膜电感器，其具有轭，其中一个或多个层叠，以及一个或多个通过轭之间的导体。叠片磁轭或磁轭有助于减少涡流和/或磁滞损耗。

33. 发明申请

US20130314192A1 INDUCTOR WITH STACKED CONDUCTORS 有权
标题翻译：带导体的电感器
公开(公告)号：US20130314192A1
公开(公告)日：2013-11-28
申请号：US13477978
申请日：2012-05-22
申请人： Robert E. Fontana, JR. , Philipp Herget , Eugene J. O'Sullivan , Lubomyr T. Romankiw , Naigang Wang , Bucknell C. Webb
发明人： Robert E. Fontana, JR. , Philipp Herget , Eugene J. O'Sullivan , Lubomyr T. Romankiw , Naigang Wang , Bucknell C. Webb
IPC分类号： H01F27/28
CPC分类号： H01F27/2804 , H01F5/00 , H01F17/0013 , H01F2017/0066 , H01F2017/0086 , H01F2027/2809 , H01L28/10
摘要： A thin film coupled inductor, a thin film spiral inductor, and a system that includes an electronic device and a power supply or power converter incorporating one or more such inductors. A thin film coupled inductor includes a wafer substrate; a bottom yoke comprising a magnetic material above the wafer substrate; a first insulating layer above the bottom yoke; a first conductor above the bottom yoke and separated therefrom by the first insulating layer; a second insulating layer above the first conductor; a second conductor above the second insulating layer; a third insulating layer above the second conductor; and a non-planar top yoke above the third insulating layer, the top yoke comprising a magnetic material.
摘要翻译：薄膜耦合电感器，薄膜螺旋电感器以及包括电子器件和并入一个或多个此类电感器的电源或功率转换器的系统。薄膜耦合电感器包括晶片衬底; 底部轭，其包括晶片衬底上方的磁性材料; 在底部轭上方的第一绝缘层; 第一导体，位于底部磁轭之上并由第一绝缘层分离; 在所述第一导体上方的第二绝缘层; 在第二绝缘层上方的第二导体; 在第二导体上方的第三绝缘层; 以及在第三绝缘层上方的非平面顶部磁轭，顶部磁轭包括磁性材料。

34. 发明申请

US20130176095A1 INDUCTOR WITH LAMINATED YOKE 有权
标题翻译：带有层压板的电感器
公开(公告)号：US20130176095A1
公开(公告)日：2013-07-11
申请号：US13347571
申请日：2012-01-10
申请人： Robert E. Fontana, JR. , William J. Gallagher , Philipp Herget , Eugene J. O'Sullivan , Lubomyr T. Romankiw , Naigang Wang , Bucknell C. Webb
发明人： Robert E. Fontana, JR. , William J. Gallagher , Philipp Herget , Eugene J. O'Sullivan , Lubomyr T. Romankiw , Naigang Wang , Bucknell C. Webb
IPC分类号： H01F27/245 , H01F41/00
CPC分类号： H01F41/042 , H01F27/2804 , H01F41/046 , H01F2017/0066 , H01F2027/348
摘要： A thin film inductor having yokes, one or more of which is laminated, and one or more conductors passing between the yokes. The laminated yoke or yokes help reduce eddy currents and/or hysteresis losses.
摘要翻译：一种薄膜电感器，其具有轭，其中一个或多个层叠，以及一个或多个通过轭之间的导体。叠片磁轭或磁轭有助于减少涡流和/或磁滞损耗。

35. 发明申请

US20120217590A1 Filling Narrow Openings Using Ion Beam Etch 有权
标题翻译：使用离子束蚀刻填充狭窄的开口
公开(公告)号：US20120217590A1
公开(公告)日：2012-08-30
申请号：US13036113
申请日：2011-02-28
申请人： Katherina E. Babich , Alessandro C. Callegari , Christopher D. Sheraw , Eugene J. O'Sullivan
发明人： Katherina E. Babich , Alessandro C. Callegari , Christopher D. Sheraw , Eugene J. O'Sullivan
IPC分类号： H01L29/78 , H01L21/4763
CPC分类号： H01L29/7833 , H01L21/28088 , H01L21/32136 , H01L21/32137 , H01L29/42372 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening. Furthermore, the method includes performing a first angled etching process to at least partially remove the first layer of first fill material from above the semiconductor device by at least partially removing a first portion of the first layer proximate an inlet of the opening without removing a second portion of the first layer proximate the bottom of said opening, and forming a second layer of second fill material above the semiconductor device by forming the second layer inside the opening and above the first layer.
摘要翻译：通常，本文公开的主题涉及现代复杂的半导体器件及其形成方法，其中可以使用多层金属填充物来填充形成在层间电介质层中的窄开口。本文公开的一种说明性方法包括在半导体衬底上形成的半导体器件的电介质材料层中形成开口，该开口具有侧壁和底表面。该方法还包括通过在开口内形成第一层并且至少在开口的侧壁和底表面上方形成在半导体器件上方形成第一填充材料层。此外，该方法包括执行第一成角度蚀刻工艺，以通过至少部分地去除开口的入口附近的第一层的第一部分，而不去除第二层第二层第一填充材料的第二层所述第一层的部分靠近所述开口的底部，并且通过在所述开口内部和所述第一层上方形成所述第二层，在所述半导体器件上方形成第二填充材料层。

36. 发明授权

US08083955B2 Selective chemical etch method for MRAM freelayers 失效
标题翻译： MRAM自由机的选择性化学蚀刻方法
公开(公告)号：US08083955B2
公开(公告)日：2011-12-27
申请号：US12245255
申请日：2008-10-03
申请人： Eugene J. O'Sullivan
发明人： Eugene J. O'Sullivan
IPC分类号： B44C1/22
CPC分类号： H01L21/32134 , B82Y25/00 , B82Y40/00 , C23F1/28 , H01F41/308 , H01L43/12
摘要： An etching process is employed to selectively pattern an exposed magnetic layer of a magnetic thin film structure. The etching process generally includes selectively patterning a magnetic film structure comprises providing a magnetic structure comprising at least one bottom magnetic layer, at least one top magnetic layer, wherein the at least one bottom magnetic layer is separated from the at least one top magnetic layer by a tunnel barrier layer; and selectively etching the top magnetic layer with an etching solution comprising at least one weakly absorbing acid, a surfactant inhibitor soluble in the at least one weakly absorbing acid, and at least one cation additive, wherein etching of the tunnel barrier layer is substantially prevented. In some embodiments, etching solution comprises at least one perfluoroalkane sulfonic acid, an alkylsulfonate salt soluble in the at least one perfluoroalkane sulfonic acid, and at least one cation additive.
摘要翻译：采用蚀刻工艺来选择性地图案化磁性薄膜结构的暴露的磁性层。蚀刻工艺通常包括选择性地构图磁膜结构，包括提供包括至少一个底部磁性层，至少一个顶部磁性层的磁性结构，其中至少一个底部磁性层与至少一个顶部磁性层通过隧道势垒层; 并且用包含至少一种弱吸收酸的蚀刻溶液，可溶于所述至少一种弱吸收酸的表面活性剂抑制剂和至少一种阳离子添加剂选择性地蚀刻顶部磁性层，其中基本上防止了隧道阻挡层的蚀刻。在一些实施方案中，蚀刻溶液包含至少一种全氟烷基磺酸，可溶于至少一种全氟烷烃磺酸的烷基磺酸盐和至少一种阳离子添加剂。

37. 发明申请

US20110127493A1 SELF ALIGNED CARBIDE SOURCE/DRAIN FET 有权
标题翻译：自对准碳源/漏极FET
公开(公告)号：US20110127493A1
公开(公告)日：2011-06-02
申请号：US12627120
申请日：2009-11-30
申请人： Cyril Cabral, JR. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
发明人： Cyril Cabral, JR. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/16 , H01L29/1602 , H01L51/0048 , H01L51/0541 , H01L51/105
摘要： A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.
摘要翻译：场效应晶体管包括金属碳化物源部分，金属碳化物漏极部分，将金属碳化物源部分与金属碳化物部分分离的绝缘碳部分，形成在绝缘和碳部分上的纳米结构，并将金属碳化物源部分连接到金属碳化物排出部分和形成在绝缘碳部分的至少一部分和至少一部分纳米结构上的栅堆叠。

38. 发明申请

US20100252775A1 METHOD FOR FORMING AN INDIUM CAP LAYER 失效
标题翻译：形成印刷层的方法
公开(公告)号：US20100252775A1
公开(公告)日：2010-10-07
申请号：US12819697
申请日：2010-06-21
申请人： Maurice McGlashan-Powell , Eugene J. O'Sullivan , Daniel Charles Edelstein
发明人： Maurice McGlashan-Powell , Eugene J. O'Sullivan , Daniel Charles Edelstein
IPC分类号： C09K13/06 , C09K13/00
CPC分类号： C09K13/04
摘要： An indium cap layer is formed by blanket depositing indium onto a surface of metallic interconnects separated by interlayer dielectric, and then selectively chemically etching the indium located on the interlayer dielectric leaving an indium cap layer. Etchants containing a strong acid are provided for selectively removing the indium.
摘要翻译：通过在由层间电介质分离的金属互连件的表面上覆盖沉积铟，然后选择性地化学蚀刻位于层间电介质上的铟而形成铟盖层，留下铟盖层。提供含有强酸的蚀刻剂用于选择性地除去铟。

39. 发明授权

US07115996B2 Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped 有权
公开(公告)号：US07115996B2
公开(公告)日：2006-10-03
申请号：US10852142
申请日：2004-05-25
申请人： Daniel C. Edelstein , Sung Kwon Kang , Maurice McGlashan-Powell , Eugene J. O'Sullivan , George F. Walker
发明人： Daniel C. Edelstein , Sung Kwon Kang , Maurice McGlashan-Powell , Eugene J. O'Sullivan , George F. Walker
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76849 , H01L21/2885 , H01L21/76856 , H01L21/76858 , H01L21/76862 , H01L23/53238 , H01L24/11 , H01L2224/0401 , H01L2224/04042 , H01L2224/05546 , H01L2224/13099 , H01L2224/45144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/15747 , H05K3/244 , H01L2924/00
摘要： A method to selectively cap interconnects with indium or tin bronzes and copper oxides thereof is provided. The invention also provides the interconnect and copper surfaces so formed.

40. 发明授权

US06784088B2 Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped 有权
标题翻译：选择性地与铟或锡青铜和/或其氧化物覆盖互连的方法以及如此封闭的互连
公开(公告)号：US06784088B2
公开(公告)日：2004-08-31
申请号：US10345288
申请日：2003-01-16
申请人： Daniel C. Edelstein , Sung Kwon Kang , Maurice McGlashan-Powell , Eugene J. O'Sullivan , George F. Walker
发明人： Daniel C. Edelstein , Sung Kwon Kang , Maurice McGlashan-Powell , Eugene J. O'Sullivan , George F. Walker
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/2885 , H01L21/76856 , H01L21/76858 , H01L21/76862 , H01L23/53238 , H01L24/11 , H01L2224/0401 , H01L2224/04042 , H01L2224/05546 , H01L2224/13099 , H01L2224/45144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/15747 , H05K3/244 , H01L2924/00
摘要： A method to selectively cap a cooper BEOL terminal pad with a Cu/Sn/Au alloy. The method includes providing one or more Cu BEOL terminal pads and coating the pads with a Sn coating followed by coating the Sn with a Au coating. The coated pads are then annealed to form the Cu/Sn/Au capping alloy.
摘要翻译：一种用Cu / Sn / Au合金选择性地覆盖铜合金BEOL端子焊盘的方法。该方法包括提供一个或多个Cu BEOL端子焊盘并且用焊锡涂覆Sn涂层，然后用Au涂层涂覆Sn。然后将涂覆的焊盘退火以形成Cu / Sn / Au封盖合金。

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