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    • 31. 发明授权
    • Josephson junctions and process for making same
    • 约瑟夫逊路口和制作过程
    • US5821557A
    • 1998-10-13
    • US676477
    • 1996-07-08
    • Shinji NagamachiMasahiro UedaKei ShinadaMitsuyoshi Yoshii
    • Shinji NagamachiMasahiro UedaKei ShinadaMitsuyoshi Yoshii
    • H01L39/22H01L39/24
    • H01L39/223H01L39/2493Y10S505/817Y10S505/832Y10S505/874
    • A Josephson junction includes a substrate, a first superconducting layer, a second superconducting layer transversely overlaid on the first layer with an insulating layer interposed therebetween, the insulating layer is an oxide or a nitride of the superconducting material, and the insulating layer including a low oxygen- or nitrogen-concentrated area in contact with each of the first and second layers. A process for fabricating the Josephson junction includes the steps of preparing a substrate, forming a first superconducting layer, forming a second superconducting layer transversely on the first layer with an insulating layer interposed therebetween wherein the insulating layer is an oxide or nitride of the superconducting material, and injecting ion beams into the insulating layer so as to form low oxygen- or nitrogen-concentrated area linking the first and second layers.
    • 约瑟夫逊结包括衬底,第一超导层,横向覆盖在第一层上的第二超导层,绝缘层介于其间,绝缘层是超导材料的氧化物或氮化物,并且绝缘层包括低 氧或氮浓缩区域与第一和第二层中的每一个接触。 制造约瑟夫逊结的方法包括以下步骤:准备衬底,形成第一超导层,在第一层上横向形成第二超导层,绝缘层置于其间,其中绝缘层是超导材料的氧化物或氮化物 并且将离子束注入绝缘层中以形成连接第一层和第二层的低氧或氮浓集区域。
    • 33. 发明授权
    • Output buffer circuit having output bouncing controlled circuits
    • 输出缓冲电路,具有输出弹跳控制电路
    • US5323070A
    • 1994-06-21
    • US821941
    • 1992-01-17
    • Masahiro UedaIchiro Tomioka
    • Masahiro UedaIchiro Tomioka
    • H03K17/16H03K17/687H03K19/003H03K19/017H03K19/0175H03K19/0944H03K19/092
    • H03K19/01721H03K19/00361H03K19/09448
    • A first output buffer having a large current driving capability and a second output buffer having a small current driving capability are connected in parallel between an input terminal and an external lead. The first and second output buffers each includes two CMOS inverters connected in series between the input terminal and the external lead. The P-channel and N-channel MOSFETs of the two CMOS inverters in the second output buffer have gate widths smaller than each of the P-channel and N-channel MOSFETs, respectively, of the two CMOS inverters in the first output buffer. Also disclosed is an output buffer having P-channel and N-channel MOSFETs arranged as a CMOS inverter, but with a base of a first bipolar transistor connected to a source of the N-channel MOSFET. An emitter of the first bipolar transistor is connected to ground and its collector is connected to an output of the output buffer. A base of a second bipolar transistor is connected to an output of the CMOS inverter and its emitter is connected to the output of the output buffer. An input of the output buffer is supplied to an input of the CMOS inverter. Another transistor is connected between the output of the output buffer and ground and is responsive to the input of the output buffer.
    • 具有大电流驱动能力的第一输出缓冲器和具有小电流驱动能力的第二输出缓冲器并联连接在输入端和外部引线之间。 第一和第二输出缓冲器各自包括串联连接在输入端和外部引线之间的两个CMOS反相器。 第二输出缓冲器中的两个CMOS反相器的P沟道和N沟道MOSFET分别具有比第一输出缓冲器中的两个CMOS反相器的P沟道和N沟道MOSFET中的每一个的栅极宽度小的栅极宽度。 还公开了具有布置为CMOS反相器但具有连接到N沟道MOSFET的源极的第一双极晶体管的基极的P沟道和N沟道MOSFET的输出缓冲器。 第一双极晶体管的发射极连接到地,其集电极连接到输出缓冲器的输出端。 第二双极晶体管的基极连接到CMOS反相器的输出,其发射极连接到输出缓冲器的输出端。 输出缓冲器的输入被提供给CMOS反相器的输入。 另一个晶体管连接在输出缓冲器的输出和地之间,并响应于输出缓冲器的输入。
    • 35. 发明授权
    • High speed BiCMOS logic circuit
    • 高速BICMOS逻辑电路
    • US5164617A
    • 1992-11-17
    • US703870
    • 1991-05-23
    • Toshiaki HanibuchiMasahiro Ueda
    • Toshiaki HanibuchiMasahiro Ueda
    • H01L21/8249H01L27/06H03K17/04H03K17/567H03K19/013H03K19/08H03K19/0944
    • H01L27/0623H03K19/0136H03K19/09448
    • A signal applied through a signal input terminal is logically processed by a logic circuit such as a CMOS inverter and the processed signal is supplied from the signal output terminal. A pinch resistor has a resistance value controlled in accordance with a variation of a voltage at the signal output terminal. Specifically, the pinch resistor has a higher resistance value at an initial stage in the switching operation in which an output from the logic circuit lowers from a logical high level to a logical low level, and supplies a large base current to a bipolar transistor. At a later stage in the switching operation, the pinch resistor has a small resistance value, so that a residual charge in the signal output terminal and a base charge in the bipolar transistor are rapidly emitted through the pinch resistor. Thus, the resistance value of the pinch resistor is always maintained at an optimum value, which increases a speed of the switching operation of the logic circuit.
    • 通过信号输入端施加的信号由CMOS反相器等逻辑电路进行逻辑处理,从信号输出端提供处理后的信号。 夹持电阻器具有根据信号输出端子处的电压变化而控制的电阻值。 具体地说,在逻辑电路的输出从逻辑高电平降低到逻辑低电平的开关动作中,钳位电阻在初始阶段具有较高的电阻值,并向双极型晶体管提供较大的基极电流。 在开关操作的稍后阶段,夹持电阻器具有小的电阻值,使得信号输出端子中的剩余电荷和双极晶体管中的基极电荷通过夹持电阻器快速发射。 因此,夹持电阻器的电阻值始终保持在最佳值,这增加了逻辑电路的开关操作速度。