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31. 发明授权

US07268632B2 Structure and method for providing gate leakage isolation locally within analog circuits 失效
标题翻译：在模拟电路中局部提供栅极泄漏隔离的结构和方法
公开(公告)号：US07268632B2
公开(公告)日：2007-09-11
申请号：US11163013
申请日：2005-09-30
申请人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Stephen D. Wyatt
发明人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Stephen D. Wyatt
IPC分类号： H03L7/00 , H03L7/099 , H03B5/18
CPC分类号： H03L7/093 , H03L7/0891
摘要： A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.
摘要翻译：提供了一种用于锁相环的环路滤波器，包括并联耦合以形成环路滤波器的一组电容器组，以及用于识别和隔离有缺陷的电容器组的检测电路。根据本发明实施例的用于提供用于锁相环的环路滤波器的方法包括以下步骤：使用并联耦合的一组电容器组形成环路滤波器，检测该组中的任何有缺陷的电容器组电容器组，隔离每个有缺陷的电容器组，提供一组冗余电容器组，并从冗余电容器组组中的冗余电容器组替换每个有缺陷的电容器组。

32. 发明申请

US20080244479A1 STRUCTURE FOR INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES 有权
标题翻译：内部RC功率分配结构用于模拟电源的噪声滤波
公开(公告)号：US20080244479A1
公开(公告)日：2008-10-02
申请号：US12053958
申请日：2008-03-24
申请人： Anthony R. BONACCIO , Hayden C. Cranford , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
发明人： Anthony R. BONACCIO , Hayden C. Cranford , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
IPC分类号： G06F17/50
CPC分类号： G05F1/56
摘要： A design structure for intrinsic RC power distribution for noise filtering of analog supplies. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a voltage regulator; a variable resistor coupled to the voltage regulator; and a performance monitor and control circuit providing a feedback loop to the variable resistor.
摘要翻译：用于模拟电源噪声滤波的固有RC功率分配的设计结构。该设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。设计结构包括电压调节器; 耦合到电压调节器的可变电阻器; 以及向可变电阻器提供反馈回路的性能监视和控制电路。

33. 发明授权

US07000214B2 Method for designing an integrated circuit having multiple voltage domains 失效
标题翻译：用于设计具有多个电压域的集成电路的方法
公开(公告)号：US07000214B2
公开(公告)日：2006-02-14
申请号：US10707068
申请日：2003-11-19
申请人： Joseph A. Iadanza , Raminderpal Singh , Sebastian T. Ventrone , Ivan L. Wemple
发明人： Joseph A. Iadanza , Raminderpal Singh , Sebastian T. Ventrone , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.
摘要翻译：一种用于设计具有多个电压域的集成电路的方法，包括：（a）从包含在高级设计文件中的信息，定义全局连接声明和电压域连接声明的高级设计文件生成逻辑集成电路设计; （b）基于逻辑集成电路设计，优选组件文件中的信息和电压域定义文件中的信息，将逻辑集成电路设计合成为合成集成电路设计; （c）基于电压域定义文件和设计约束文件中的信息从合成的集成电路设计中产生噪声模型; 和（d）根据设计约束文件中的约束和电路级配置文件中的约束模拟噪声模型，以确定合成的集成电路设计是否满足预定的噪声模拟目标。

34. 发明授权

US07257788B2 Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits 有权
标题翻译：用于将全局时钟选通电路转换为本地时钟门控电路的方法和装置
公开(公告)号：US07257788B2
公开(公告)日：2007-08-14
申请号：US10904397
申请日：2004-11-08
申请人： Allen P. Haar , Joseph A. Iadanza , Sebastian T. Ventrone , Ivan L. Wemple
发明人： Allen P. Haar , Joseph A. Iadanza , Sebastian T. Ventrone , Ivan L. Wemple
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.
摘要翻译：公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

35. 发明申请

US20080240222A1 SYSTEM AND METHOD FOR BALANCING DELAY OF SIGNAL COMMUNICATION PATHS THROUGH WELL VOLTAGE ADJUSTMENT 有权
标题翻译：通过良好的电压调整来平衡信号通信的延迟的系统和方法
公开(公告)号：US20080240222A1
公开(公告)日：2008-10-02
申请号：US12136359
申请日：2008-06-10
申请人： Hayden C. Cranford , Joseph A. Iadanza , Sebastian T. Ventrone
发明人： Hayden C. Cranford , Joseph A. Iadanza , Sebastian T. Ventrone
IPC分类号： G01R31/28 , H03K5/159 , H03H7/40 , H03H7/30
CPC分类号： H03K5/133 , H03K2005/00032
摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.
摘要翻译：在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。

36. 发明申请

US20080046772A1 SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION 审中-公开
标题翻译：改变噪声减少的不活动时钟边缘
公开(公告)号：US20080046772A1
公开(公告)日：2008-02-21
申请号：US11457916
申请日：2006-07-17
申请人： Igor Arsovski , Joseph A. Iadanza , Jason M. Norman , Hemen Shah , Sebastian T. Ventrone
发明人： Igor Arsovski , Joseph A. Iadanza , Jason M. Norman , Hemen Shah , Sebastian T. Ventrone
IPC分类号： G06F1/00
CPC分类号： G06F1/10
摘要： A method and system for reducing clock noises are disclosed. A clock signal includes active edges and inactive edges. Inactive edges produce clock noise but are not critical to the functionality of the clock signal. That is, only active edges are critical to proper timing of an integrated circuit (IC). As such, inactive edges of clock signals to clocked elements of an IC may be shifted to be misaligned to one another. As a consequence, peak noise produced by the inactive edges will be spread over a large area and therefore will be reduced in amplitude.
摘要翻译：公开了一种减少时钟噪声的方法和系统。时钟信号包括有效边沿和非活动边沿。无效边沿产生时钟噪声，但并不对时钟信号的功能至关重要。也就是说，只有有效边沿对于集成电路（IC）的正确定时至关重要。因此，到IC的时钟元件的时钟信号的无效边沿可能被移位以彼此不对准。结果，由无源边缘产生的峰值噪声将在大面积上扩展，因此幅度将被减小。

37. 发明授权

US06545521B2 Low skew, power sequence independent CMOS receiver device 失效
标题翻译：低偏移，电源顺序独立的CMOS接收器件
公开(公告)号：US06545521B2
公开(公告)日：2003-04-08
申请号：US09895778
申请日：2001-06-29
申请人： Bret R. Dale , Joseph A. Iadanza , Douglas W. Stout , Sebastian T. Ventrone , Hongfei Wu
发明人： Bret R. Dale , Joseph A. Iadanza , Douglas W. Stout , Sebastian T. Ventrone , Hongfei Wu
IPC分类号： H03L500
CPC分类号： H04L25/0292 , H03K19/00315 , H04L25/0266 , H04L25/0272
摘要： The present invention provides a receiver device having multiple voltage supplies that allows the output stage of the receiver device to go to a safe state whenever its voltage is disconnected or powered-down, independent of any of its normal control circuits. Furthermore, the isolation of the multiple voltage supplies provides a low skew at the output of the receiver device.
摘要翻译：本发明提供了一种具有多个电压源的接收机设备，每当其电压断开或掉电时，接收机设备的输出级都能够进入安全状态，独立于其任何正常的控制电路。此外，多个电压源的隔离在接收器件的输出处提供低偏移。

38. 发明授权

US06487701B1 System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technology 失效
标题翻译：通过液晶半导体技术中的阈值电压偏移进行交流性能调谐的系统和方法
公开(公告)号：US06487701B1
公开(公告)日：2002-11-26
申请号：US09711744
申请日：2000-11-13
申请人： Alvar A. Dean , Jerry D. Hayes , Joseph A. Iadanza , Emory D. Keller , Sebastian T. Ventrone
发明人： Alvar A. Dean , Jerry D. Hayes , Joseph A. Iadanza , Emory D. Keller , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G01R31/3163 , G01R31/2891
摘要： A system and method are described for separating the bulk connections for FETs on a semiconductor wafer from the supply rails, testing the wafer to determine if a shift in the threshold voltage, VT, of certain devices within the wafer, as defined by the bulk-wells, can remove an AC defect in the IC circuit, and tailoring the voltage or voltages applied to the bulk nodes, post-manufacture, such that the integrated circuit meets its performance targets or is sorted to a more valuable performance level. The method requires generating a gate level netlist of the IC's circuitry and performing timing calculations on these circuit netlists using static timing analyses, functional delay simulations, circuit activity analyses, and functional performance testing. The failures are then correlated to respective IC circuits, worst case slack circuits are investigated, and proposed changes to the threshold voltages are employed in the hardware.
摘要翻译：描述了一种系统和方法，用于将半导体晶片上的FET的体连接与电源轨分开，测试晶片以确定晶片内的某些器件的阈值电压VT是否偏移，孔可以去除IC电路中的AC缺陷，并且定制施加到散装节点的电压或电压，后制造，使得集成电路满足其性能目标或被分类到更有价值的性能水平。该方法需要生成IC电路的门级网表，并使用静态时序分析，功能延迟模拟，电路活动分析和功能性能测试来对这些电路网表执行定时计算。然后将故障与相应的IC电路相关联，最坏情况下调查松弛电路，并且在硬件中采用提出的阈值电压的改变。

39. 发明授权

US07743270B2 Assigning clock arrival time for noise reduction 失效
标题翻译：为降噪分配时钟到达时间
公开(公告)号：US07743270B2
公开(公告)日：2010-06-22
申请号：US11530544
申请日：2006-09-11
申请人： Igor Arsovski , Joseph A. Iadanza , Jason M. Norman , Sebastian T. Ventrone
发明人： Igor Arsovski , Joseph A. Iadanza , Jason M. Norman , Sebastian T. Ventrone
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00
CPC分类号： G06F1/04 , G06F1/10 , G06F17/5031 , G06F17/505 , G06F2217/62
摘要： A method, system and computer program product reducing clock noise generated by clock signals in an integrated circuit (IC) are disclosed. Conventional IC design attempts to ensure coincident clock active edge arrival times for all clocked elements. The coincident active clock edges generate coincident noise currents, which elevates the total noise current. The current invention assigns clock arrival times for clocked elements of an IC based on a desired clock arrival time distribution such that active clock edges are not coincident. As a consequence, the total noise would be spread over a large portion of the clock cycle, thus reducing the noise magnitude substantially.
摘要翻译：公开了减少由集成电路（IC）中的时钟信号产生的时钟噪声的方法，系统和计算机程序产品。传统IC设计尝试确保所有时钟元件的重合时钟主动边沿到达时间。重合的有效时钟边沿产生一致的噪声电流，这提高了总的噪声电流。本发明基于期望的时钟到达时间分布来为IC的时钟元件分配时钟到达时间，使得活动时钟边缘不一致。因此，总噪声将在时钟周期的大部分时间内扩展，从而大大降低噪声幅度。

40. 发明申请

US20090102529A1 SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION 审中-公开
标题翻译：改变噪声减少的不活动时钟边缘
公开(公告)号：US20090102529A1
公开(公告)日：2009-04-23
申请号：US11876871
申请日：2007-10-23
申请人： Igor Arsovski , Joseph A. Iadanza , Jason M. Norman , Hemen Shah , Sebastian T. Ventrone
发明人： Igor Arsovski , Joseph A. Iadanza , Jason M. Norman , Hemen Shah , Sebastian T. Ventrone
IPC分类号： H03K3/017
CPC分类号： H03K3/84 , H03K7/08
摘要： An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: multiple clocked elements; a clock signal source providing clock signals to the multiple clocked elements; and a clock shifting means coupled between the clock signal source and each of the multiple clocked elements; wherein the clock shifting means shifts clock signals of the multiple clocked elements such that the clock signals of the multiple clocked elements have aligned active edges and misaligned inactive edges to reduce the clock noise generated by the inactive edges of the clock signals.
摘要翻译：公开了集成电路和设计结构。集成电路可以包括：多个时钟元件; 时钟信号源，向多个时钟元件提供时钟信号; 以及时钟移位装置，其耦合在所述时钟信号源与所述多个时钟元件中的每一个之间; 其中所述时钟移位装置移动所述多个时钟元件的时钟信号，使得所述多个时钟元件的时钟信号具有对准的有源边沿和未对准的非有效边沿，以减少由所述时钟信号的不活动边缘产生的时钟噪声。

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