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31. 发明授权

US08250265B2 Method and system for storing memory compressed data onto memory compressed disks 有权
标题翻译：将内存压缩数据存储到内存压缩磁盘上的方法和系统
公开(公告)号：US08250265B2
公开(公告)日：2012-08-21
申请号：US13077667
申请日：2011-03-31
申请人： Caroline Benveniste , Vittorio Castelli , Peter A. Franaszek
发明人： Caroline Benveniste , Vittorio Castelli , Peter A. Franaszek
IPC分类号： G06F13/38 , G06F13/00
CPC分类号： G06F3/0608 , G06F3/064 , G06F3/0676 , G06F12/08 , G06F2212/401
摘要： A method of transmitting compressed data from a main memory to an input/output adaptor (IOA)/input/output processor (IOP), includes sending compressed memory directory information to the IOA/IOP and copying a content of the memory to the IOA/IOP using a direct memory access (DMA) operation, without decompressing the data.
摘要翻译：将压缩数据从主存储器传送到输入/输出适配器（IOA）/输入/输出处理器（IOP）的方法包括将压缩存储器目录信息发送到IOA / IOP并将存储器的内容复制到IOA / IOP使用直接存储器访问（DMA）操作，而不解压缩数据。

32. 发明授权

US08234229B2 Method and apparatus for prediction of computer system performance based on types and numbers of active devices 有权
标题翻译：基于有源设备的类型和数量来预测计算机系统性能的方法和装置
公开(公告)号：US08234229B2
公开(公告)日：2012-07-31
申请号：US09916935
申请日：2001-07-27
申请人： Vittorio Castelli , Peter A. Franaszek , Joy Aloysius Thomas
发明人： Vittorio Castelli , Peter A. Franaszek , Joy Aloysius Thomas
IPC分类号： G06F15/18 , G06F3/00 , G06F1/00 , G06F17/50
CPC分类号： H04L41/00 , H04L41/147 , H04L43/00 , H04L43/16
摘要： A method for predicting a subsequent resource utilization in a computer system having a plurality of devices includes the step of monitoring, over a period of time, a contemporaneous resource utilization and a number of active devices to obtain monitored values of the contemporaneous resource utilization and the number of active devices. The subsequent resource utilization is predicted, based upon the monitored values of the contemporaneous resource utilization and the number of active devices. Additionally, methods are described herein for identifying resource saturation and predicting the effects of adding a new device in a computer system.
摘要翻译：一种用于预测具有多个设备的计算机系统中的后续资源利用的方法包括以下步骤：在一段时间内监视同时期的资源利用和多个活动设备，以获得当前资源利用的监视值，并且有效设备数。基于当前资源利用率和活动设备数量的监测值，预测后续的资源利用率。此外，本文描述了用于识别资源饱和度并预测在计算机系统中添加新设备的效果的方法。

33. 发明授权

US08185899B2 Prediction based priority scheduling 有权
标题翻译：基于预测的优先级调度
公开(公告)号：US08185899B2
公开(公告)日：2012-05-22
申请号：US11683147
申请日：2007-03-07
申请人： David M. Daly , Peter A. Franaszek , Luis A. Lastras-Montano
发明人： David M. Daly , Peter A. Franaszek , Luis A. Lastras-Montano
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： Systems and methods are provided that schedule task requests within a computing system based upon the history of task requests. The history of task requests can be represented by a historical log that monitors the receipt of high priority task request submissions over time. This historical log in combination with other user defined scheduling rules is used to schedule the task requests. Task requests in the computer system are maintained in a list that can be divided into a hierarchy of queues differentiated by the level of priority associated with the task requests contained within that queue. The user-defined scheduling rules give scheduling priority to the higher priority task requests, and the historical log is used to predict subsequent submissions of high priority task requests so that lower priority task requests that would interfere with the higher priority task requests will be delayed or will not be scheduled for processing.
摘要翻译：提供了系统和方法，其基于任务请求的历史在计算系统内调度任务请求。任务请求的历史可以由历史日志表示，该日志监视随时间的收到高优先级任务请求提交。该历史日志与其他用户定义的调度规则相结合用于调度任务请求。计算机系统中的任务请求被维护在列表中，该列表可以被划分成由包含在该队列内的任务请求所关联的优先级所区分的队列层次。用户定义的调度规则给予较高优先级任务请求的调度优先级，并且使用历史日志来预测高优先级任务请求的后续提交，使得将干扰较高优先级任务请求的较低优先级任务请求将被延迟或不会安排进行处理。

34. 发明授权

US08136106B2 Learning and cache management in software defined contexts 失效
标题翻译：在软件定义的上下文中学习和缓存管理
公开(公告)号：US08136106B2
公开(公告)日：2012-03-13
申请号：US12119912
申请日：2008-05-13
申请人： Peter A. Franaszek , Luis Alfonso Lastras Montaño , R. Brett Tremaine
发明人： Peter A. Franaszek , Luis Alfonso Lastras Montaño , R. Brett Tremaine
IPC分类号： G06F9/45
CPC分类号： G06F8/4442 , G06F12/0862 , G06F2212/1021 , G06F2212/6028
摘要： A system includes a processor, a memory, a cache, program software, and a marker management engine. The software includes at least one marker. Each marker is a computer instruction and marks distinct computer code sections in the software. The engine (a) determines whether one of the at least one marker is executed during the execution of the program software, (b) monitors data accesses by the at least one processor to the at least one cache and the main memory, (c) stores at least one of the monitored data accesses in a pre-defined location in the main memory, and (d) optimizes only the computer code section indicated by the determined marker of the program software executed by the at least one processor based on the stored data accesses.
摘要翻译：系统包括处理器，存储器，高速缓存，程序软件和标记管理引擎。软件包括至少一个标记。每个标记是一个计算机指令，并在软件中标记不同的计算机代码段。引擎（a）确定在执行程序软件期间是否执行至少一个标记之一，（b）监视至少一个处理器对至少一个高速缓存和主存储器的数据访问，（c）将至少一个所监视的数据访问存储在主存储器中的预定义位置中，以及（d）仅基于存储的所述至少一个处理器执行的由所确定的程序软件的标记指示的计算机代码段优化数据访问。

35. 发明申请

US20090320006A1 LEARNING AND CACHE MANAGEMENT IN SOFTWARE DEFINED CONTEXTS 失效
标题翻译：软件定义的内容中的学习和高速缓存管理
公开(公告)号：US20090320006A1
公开(公告)日：2009-12-24
申请号：US12119912
申请日：2008-05-13
申请人： Peter A. Franaszek , Luis Alfonso Lastras Montano , R. Brett Tremaine
发明人： Peter A. Franaszek , Luis Alfonso Lastras Montano , R. Brett Tremaine
IPC分类号： G06F9/45 , G06F12/00 , G06F12/08
CPC分类号： G06F8/4442 , G06F12/0862 , G06F2212/1021 , G06F2212/6028
摘要： A exemplary system and method are provided for learning and cache management in software defined contexts. Exemplary embodiments of the present invention described herein address the problem of the data access wall resulting from processor stalls due to the increasing discrepancies between processor speed and the latency of access to data that is not stored in the immediate vicinity of the processor requesting the data.
摘要翻译：提供了用于在软件定义的上下文中学习和缓存管理的示例性系统和方法。本文描述的本发明的示例性实施例解决了由于处理器速度与未存储在请求数据的处理器紧邻附近的数据的访问等待时间之间的差异而导致的处理器停顿所导致的数据访问壁的问题。

36. 发明申请

US20080307188A1 Management of Guest OS Memory Compression In Virtualized Systems 审中-公开
标题翻译：虚拟化系统中客户操作系统内存压缩的管理
公开(公告)号：US20080307188A1
公开(公告)日：2008-12-11
申请号：US11758715
申请日：2007-06-06
申请人： Peter A. Franaszek , Dan E. Poff
发明人： Peter A. Franaszek , Dan E. Poff
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F9/5016 , G06F9/5077 , G06F2212/401
摘要： The present invention provides a system and method for managing compression memory in a computer system. This system includes a hypervisor having means for identifying a operating system having a plurality of memory pages allocated, means for counting the number of a plurality of memory pages allocated, and means for counting a number of free space pages in the compressed memory. The hypervisor further includes means for determining if the number of free space pages is less than a predetermined threshold, and means for increasing the number of free space pages if less than a predetermined threshold.
摘要翻译：本发明提供一种用于管理计算机系统中的压缩存储器的系统和方法。该系统包括管理程序，其具有用于识别具有分配的多个存储器页面的操作系统的装置，用于对分配的多个存储器页面的数量进行计数的装置，以及用于对压缩存储器中的可用空间页数进行计数的装置。管理程序还包括用于确定可用空间页数是否小于预定阈值的装置，以及用于如果小于预定阈值则增加可用空间页数的装置。

37. 发明授权

US07386679B2 System, method and storage medium for memory management 失效
标题翻译：用于内存管理的系统，方法和存储介质
公开(公告)号：US07386679B2
公开(公告)日：2008-06-10
申请号：US10709128
申请日：2004-04-15
申请人： Peter A. Franaszek , Luis A. Lastras
发明人： Peter A. Franaszek , Luis A. Lastras
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0895 , G06F2212/1024 , G06F2212/502 , G06F2212/6022 , G06F2212/6024
摘要： A system for memory management including a tag controlled buffer in communication with a memory device. The memory device includes a plurality of pages divided into a plurality of individually addressable lines. The tag controlled buffer includes a prefetch buffer including at least one of the individually addressable lines from the memory device. The tag controlled buffer also includes a tag cache in communication with the prefetch buffer. The tag cache includes a plurality of tags, where each tag is associated with one of the pages in the memory device and each tag includes a pointer to at least one of the lines in the prefetch buffer. Access to the lines in the prefetch buffer is controlled by the tag cache.
摘要翻译：一种用于存储器管理的系统，包括与存储器件通信的标签控制缓冲器。存储装置包括被分成多个可单独寻址的行的多个页面。标签控制缓冲器包括预取缓冲器，其包括来自存储器装置的至少一个可单独寻址的线路。标签控制缓冲器还包括与预取缓冲器通信的标签缓存。标签缓存包括多个标签，其中每个标签与存储器设备中的一个页面相关联，并且每个标签包括指向预取缓冲器中的至少一行的指针。访问预取缓冲区中的行由标记缓存控制。

38. 发明授权

US06993458B1 Method and apparatus for preprocessing technique for forecasting in capacity management, software rejuvenation and dynamic resource allocation applications 失效
标题翻译：预处理技术在容量管理，软件复兴和动态资源分配应用中的预测方法和装置
公开(公告)号：US06993458B1
公开(公告)日：2006-01-31
申请号：US09706737
申请日：2000-11-07
申请人： Vittorio Castelli , Peter A. Franaszek
发明人： Vittorio Castelli , Peter A. Franaszek
IPC分类号： G06F11/30
CPC分类号： G06F11/008
摘要： A system and method preprocesses data, in a computer system where forecasting of computing resources is performed based on past and present observations of measurements related to the resources. The preprocessing includes decomposing the past and present observations into a smooth time sequence, a jump time sequence, a noise time sequence and a spike time sequence. The method (and system) includes detecting the spikes in a signal representing the measurements, detecting the jumps in the signal, removing spikes and jumps from the signal, and removing the noise from the signal, to obtain a smooth version of the signal.
摘要翻译：系统和方法在计算机系统中预处理数据，其中基于与资源相关的测量的过去和当前观察来执行计算资源的预测。预处理包括将过去和现在的观测值分解为平滑时间序列，跳跃时间序列，噪声时间序列和尖峰时间序列。方法（和系统）包括检测表示测量的信号中的尖峰，检测信号中的跳跃，从信号中去除尖峰和跳跃，以及从信号中去除噪声，以获得信号的平滑版本。

39. 发明授权

US06847315B2 Nonuniform compression span 失效
标题翻译：不均匀的压缩范围
公开(公告)号：US06847315B2
公开(公告)日：2005-01-25
申请号：US10417707
申请日：2003-04-17
申请人： Vittorio Castelli , Peter A. Franaszek
发明人： Vittorio Castelli , Peter A. Franaszek
IPC分类号： G06F12/08 , H03M7/30 , H03M7/00
CPC分类号： H03M7/3088 , G06F12/08 , G06F12/0802 , G06F2212/401
摘要： A method and structure stores and/or transmits and receives data in compressed form. Retrieval latencies are reduced by selectively transmitting a portion of the data in uncompressed form. When the apparatus is part of a computer architecture supporting main memory compression, a selected L2 cache line belonging to the unit of main memory compression is kept uncompressed. To minimize decompression latency, the uncompressed L2 cache line is stored with the compressed-memory directory. Alternatively, the uncompressed L2 cache line is stored in the compressed memory together with the rest of the memory compression unit it belongs to.
摘要翻译：方法和结构以压缩形式存储和/或发送和接收数据。通过选择性地以未压缩形式传送数据的一部分来减少检索延迟。当该设备是支持主存储器压缩的计算机体系结构的一部分时，属于主存储器压缩单元的所选择的L2高速缓存行保持未压缩。为了最小化解压延迟，未压缩的L2高速缓存行与压缩内存目录一起存储。或者，未压缩的L2高速缓存行与其所属的存储器压缩单元的其余部分一起存储在压缩存储器中。

40. 发明授权

US06665787B2 Very high speed page operations in indirect accessed memory systems 失效
公开(公告)号：US06665787B2
公开(公告)日：2003-12-16
申请号：US09795414
申请日：2001-02-28
申请人： Peter A. Franaszek , Charles O. Schulz , T. Basil Smith, III , Robert B. Tremaine , Michael Wazlowski
发明人： Peter A. Franaszek , Charles O. Schulz , T. Basil Smith, III , Robert B. Tremaine , Michael Wazlowski
IPC分类号： G06F1208
CPC分类号： G06F12/1009
摘要： A computing system and method employing a processor device for generating real addresses associated with memory locations of a real memory system for reading and writing of data thereto, the system comprising: a plurality of memory blocks in the real memory system for storing data, a physical memory storage for storing the pages of data comprising one or more real memory blocks, each real memory block partitioned into one or more sectors, each comprising contiguous bytes of physical memory; a translation table structure in the physical memory storage having entries for associating a real address with sectors of the physical memory, each translation table entry including one or more pointers for pointing to a corresponding sector in its associated real memory block, the table accessed for storing data in one or more allocated sectors for memory read and write operations initiated by the processor; and, a control device for directly manipulating entries in the translation table structure for performing page operations without actually accessing physical memory data contents. In this system, the actual data of the pages involved in the operation are never accessed by the processor and therefore is never required in the memory cache hierarchy, thus eliminating the cache damage normally associated with these block operations. Further the manipulation of the translation table will involve reading and writing a few bytes to perform the operation as opposed to reading and writing the hundreds or thousands of bytes in the pages being manipulated.

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