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31. 发明授权

US07867832B2 Electrical fuse and method of making 有权
标题翻译：电熔丝及其制作方法
公开(公告)号：US07867832B2
公开(公告)日：2011-01-11
申请号：US12268549
申请日：2008-11-11
申请人： Chih-Chao Yang , Haining S. Yang
发明人： Chih-Chao Yang , Haining S. Yang
IPC分类号： H01L23/62
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing compressive stress liner material over the fuse material, and patterning the compressive stress liner material.
摘要翻译：一种半导体保险丝及其制作方法。保险丝包括熔丝元件和压缩应力衬垫，其减小了熔丝元件的电迁移电阻。该方法包括形成衬底，在衬底中形成沟槽特征，在沟槽特征中沉积熔丝材料，在熔丝材料上沉积压应力衬垫材料，以及图案化压应力衬垫材料。

32. 发明授权

US07859044B2 Partially gated FINFET with gate dielectric on only one sidewall 有权
标题翻译：部分选通FINFET，仅在一个侧壁上具有栅极电介质
公开(公告)号：US07859044B2
公开(公告)日：2010-12-28
申请号：US11782079
申请日：2007-07-24
申请人： Robert C. Wong , Haining S. Yang
发明人： Robert C. Wong , Haining S. Yang
IPC分类号： H01L29/78 , H01L27/12
CPC分类号： H01L29/66795 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1211 , H01L29/785
摘要： A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit.
摘要翻译：在至少一个半导体鳍片的侧壁上形成栅极电介质和栅极导体层。图案化栅极导体层，使得栅极电极形成在半导体鳍片的一部分的第一侧壁上，而在第一侧壁的相对侧上的第二侧壁不受栅电极控制。因此，形成了部分选通的finFET，即在第一侧壁上具有栅电极且在第二侧壁上没有栅电极的finFET。传统的双栅极finFET可以在同一衬底上与本发明的部分选通的鳍状FET形成，以在诸如SRAM电路的同一电路中提供具有不同导通电流的多个finFET。

33. 发明授权

US07842940B2 Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost 有权
标题翻译：用于形成半导体上孔（SOP）的结构和方法，用于高器件性能和低制造成本
公开(公告)号：US07842940B2
公开(公告)日：2010-11-30
申请号：US12062164
申请日：2008-04-03
申请人： Joel P. de Souza , Keith E. Fogel , Brian J. Greene , Devendra K. Sadana , Haining S. Yang
发明人： Joel P. de Souza , Keith E. Fogel , Brian J. Greene , Devendra K. Sadana , Haining S. Yang
IPC分类号： H01L31/00
CPC分类号： H01L29/32 , H01L21/0203 , H01L21/76259 , H01L29/1033 , H01L29/1083 , H01L29/16 , H01L29/78
摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.
摘要翻译：提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层。

34. 发明申请

US20100295132A1 PROGRAMMABLE PN ANTI-FUSE 有权
标题翻译：可编程PN防熔丝
公开(公告)号：US20100295132A1
公开(公告)日：2010-11-25
申请号：US12698302
申请日：2010-02-02
申请人： Ping-Chuan Wang , Robert C. Wong , Haining S. Yang
发明人： Ping-Chuan Wang , Robert C. Wong , Haining S. Yang
IPC分类号： H01L27/06 , H01L21/8234 , H01L21/326
CPC分类号： H01L27/0727 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p− substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p− substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse.
摘要翻译：在FET结构中提供可编程反熔丝的结构和方法。形成可编程反熔丝的方法包括：提供具有n +栅极叠层的p衬底; 在p衬底中注入n +源极区域和n +漏极区域; 在n +漏极区域上形成抗蚀剂掩模，同时使n +源极区域露出; 蚀刻n +源极区域以在n +源极区域中形成凹陷; 以及在n +源极区的凹槽中生长p +外延硅锗层以形成用作可编程二极管或反熔丝的pn结。

35. 发明授权

US07791109B2 Metal silicide alloy local interconnect 失效
标题翻译：金属硅化物合金局部互连
公开(公告)号：US07791109B2
公开(公告)日：2010-09-07
申请号：US11693035
申请日：2007-03-29
申请人： Clement H. Wann , Haining S. Yang
发明人： Clement H. Wann , Haining S. Yang
IPC分类号： H01L27/10 , H01L27/11 , G11C5/06 , G11C11/00 , G11C11/34
CPC分类号： H01L21/76895 , G11C11/412 , H01L27/11 , H01L27/1104 , Y10S257/903
摘要： A local interconnect is formed with a gate conductor line that has an exposed sidewall on an active area of a semiconductor substrate. The exposes sidewall comprises a silicon containing material that may form a silicide alloy upon silicidation. During a silicidation process, a gate conductor sidewall silicide alloy forms on the exposed sidewall of the gate conductor line and an active area silicide is formed on the active area. The two silicides are joined to provide an electrical connection between the active area and the gate conductor line. Multiple sidewalls may be exposed on the gate conductor line to make multiple connections to different active area silicides.
摘要翻译：局部互连形成有栅极导体线，其在半导体衬底的有源区上具有暴露的侧壁。暴露的侧壁包括可以在硅化时形成硅化物合金的含硅材料。在硅化工艺期间，在栅极导体线的暴露的侧壁上形成栅极导体侧壁硅化物合金，并且在有源区上形成有源区硅化物。两个硅化物被接合以在有源区域和栅极导体线之间提供电连接。多个侧壁可能暴露在栅极导体线上，以使多个连接到不同的有源区硅化物。

36. 发明授权

US07781847B2 Device patterned with sub-lithographic features with variable widths 失效
标题翻译：用具有可变宽度的亚光刻特征构图的装置
公开(公告)号：US07781847B2
公开(公告)日：2010-08-24
申请号：US12034972
申请日：2008-02-21
申请人： Haining S. Yang
发明人： Haining S. Yang
IPC分类号： H01L27/088
CPC分类号： H01L21/0337 , H01L21/0334 , H01L21/3086 , H01L21/3088 , H01L21/76229 , H01L21/84 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L27/1203 , Y10S438/942 , Y10S438/947 , Y10S977/887
摘要： A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls of the dummy elements and portions of the top surface of the cap layer aside from the dummy elements. Deposit a spacer layer over the device covering the patterned dummy elements and exposed surfaces of the cap layer. Etch back the spacer layer forming sidewall spacers aside from the sidewalls of the patterned dummy elements spaced above a minimum spacing and forming super-wide spacers between sidewalls of the patterned dummy elements spaced less than the minimum spacing. Strip the patterned dummy elements. Expose portions of the substrate aside from the sidewall spacers. Pattern exposed portions of the substrate by etching into the substrate.
摘要翻译：处理装置的基板的方法包括以下步骤。在基材上形成盖层。在盖层上形成虚设层，盖层具有顶表面。蚀刻虚拟层，形成具有可变宽度的图案化虚拟元件，并暴露虚拟元件的侧壁和除了虚拟元件之外的盖层的顶表面的部分。在覆盖图案化的虚拟元件和盖层的暴露表面的器件上沉积间隔层。将形成侧壁间隔物的间隔层向后蚀刻，除了图案化的虚设元件的侧壁之间间隔开最小间隔，并且在图案化的虚设元件的侧壁之间形成超宽间隔物，其间隔开小于最小间隔。剥去图案的虚拟元素。将侧衬垫的一部分露出。通过蚀刻到衬底中的衬底的图案曝光部分。

37. 发明申请

US20100207213A1 BODY CONTACTS FOR FET IN SOI SRAM ARRAY 有权
标题翻译：用于SOI SRAM阵列中的FET的身体接触
公开(公告)号：US20100207213A1
公开(公告)日：2010-08-19
申请号：US12707191
申请日：2010-02-17
申请人： Yue Tan , Zhibin Ren , Richard A. Wachnik , Haining S. Yang
发明人： Yue Tan , Zhibin Ren , Richard A. Wachnik , Haining S. Yang
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L29/7833 , H01L29/7841
摘要： Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N−, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P−) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.
摘要翻译：与SOI中的FET的浮体接触可以形成在FET的两个扩散中的一个中的一个的一部分中，其中“牺牲”的扩散部分（例如N，用于NFET）用于制造接触是不直接相邻（或在门下方）的扩散部分。这与连接的主体FET工作良好，其中扩散不会一直延伸到BOX，因此连接体（例如P-）在形成接触的扩散下延伸。示出了向6T SRAM单元的两个NFET（PG和PD）接地的示例。

38. 发明授权

US07777296B2 Nano-fuse structural arrangements having blow protection barrier spaced from and surrounding fuse link 失效
标题翻译：纳米熔丝结构布置具有隔离和围绕熔断体的防风保护栅
公开(公告)号：US07777296B2
公开(公告)日：2010-08-17
申请号：US11566865
申请日：2006-12-05
申请人： Haining S. Yang , Jack A. Mandelman
发明人： Haining S. Yang , Jack A. Mandelman
IPC分类号： H01L23/525
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/28525 , H01L21/76805 , H01L21/7682 , H01L21/76876 , H01L21/76879 , H01L23/5256 , H01L29/0673 , H01L29/0676 , H01L2221/1063 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： A nano-fuse structural arrangement, includes, for example, a semiconductor substrate having an electrically conductive region formed thereon; an electrically conductive elongated nano-structure having a maximum diameter of less than approximately 50 nm and a maximum length of approximately 250 nm and being formed on the electrically conductive region; a barrier having barrier parts completely spaced from and completely surrounding elongated outer surfaces of the nano-structure, the spaces between the barrier and surfaces consisting essentially of a vacuum and being approximately equally spaced, so that the electrically conductive elongated nano-structure is blowable responsive to an electrical current flowable there through in a range of approximately 4 μA to approximately 120 μA.
摘要翻译：纳米熔丝结构布置包括例如其上形成有导电区域的半导体衬底; 导电细长纳米结构，其具有小于约50nm的最大直径和约250nm的最大长度，并且形成在导电区域上; 阻挡层具有与纳米结构的细长外表面完全间隔开并且完全包围细长外表面的阻挡部分，阻挡层和表面之间的空间基本上由真空构成，并且大致等间隔，使得导电细长纳米结构是可发射的到大约4μA至大约120μA的范围内可流过的电流。

39. 发明申请

US20100176450A1 STRUCTURE AND METHOD OF FORMING A TRANSISTOR WITH ASYMMETRIC CHANNEL AND SOURCE/DRAIN REGIONS 有权
标题翻译：用不对称通道和源/漏区形成晶体管的结构和方法
公开(公告)号：US20100176450A1
公开(公告)日：2010-07-15
申请号：US12351263
申请日：2009-01-09
申请人： Haining S. Yang , Kangguo Cheng , Robert Wong
发明人： Haining S. Yang , Kangguo Cheng , Robert Wong
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78618 , H01L29/78684 , H01L29/78696
摘要： A semiconductor structure is described. The structure includes a semiconductor substrate having a conductive gate abutting a gate insulator for controlling conduction of a channel region; and a source region and a drain region associated with the conductive gate, where the source region includes a first material and the drain region includes a second material, and where the conductive gate is self-aligned to the first material and the second material. In one embodiment, the first material includes Si and the second material includes SiGe. A method of forming a semiconductor structure is also described. The method includes forming a pad layer on a top surface of a SOI layer of a semiconductor substrate; patterning the pad layer and a portion of the SOI layer for forming a SiGe layer; epitaxially growing the SOI layer for forming a Si layer and a SiGe layer adjacent to a sidewall of the SOI layer; selectively pulling a portion of the pad layer; forming a gate dielectric of a portion of the SiGe layer and the SOI layer; forming a gate conductor over the gate dielectric; removing the remaining of the pad layer; forming a source region in at least one of the SOI layer and the SiGe layer; and forming a drain region in at least one of the SOI layer and the SiGe layer.
摘要翻译：描述半导体结构。该结构包括具有邻接栅极绝缘体的导电栅极以控制沟道区域的导通的半导体衬底; 以及与导电栅极相关联的源极区域和漏极区域，其中源极区域包括第一材料，并且漏极区域包括第二材料，并且其中导电栅极与第一材料和第二材料自对准。在一个实施例中，第一材料包括Si，第二材料包括SiGe。还描述了形成半导体结构的方法。该方法包括在半导体衬底的SOI层的顶表面上形成焊盘层; 图案化衬垫层和用于形成SiGe层的SOI层的一部分; 外延生长用于形成Si层的SOI层和与SOI层的侧壁相邻的SiGe层; 选择性地拉动衬垫层的一部分; 形成SiGe层和SOI层的一部分的栅极电介质; 在所述栅极电介质上形成栅极导体; 去除衬垫层的剩余部分; 在所述SOI层和所述SiGe层中的至少一个中形成源区; 以及在所述SOI层和所述SiGe层中的至少一个中形成漏区。

40. 发明申请

US20100143649A1 HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD 有权
标题翻译：高比例电镀金属特征及方法
公开(公告)号：US20100143649A1
公开(公告)日：2010-06-10
申请号：US12706108
申请日：2010-02-16
申请人： Daniel C. Edelstein , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
发明人： Daniel C. Edelstein , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
IPC分类号： B32B3/10
CPC分类号： C25D5/02 , Y10T428/24331 , Y10T428/24917
摘要： Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.
摘要翻译：公开了改进的高宽比电镀金属结构（例如，铜或铜合金互连，例如线的后端（BEOL）或线的中间（MOL）接触）的实施例，其中电镀金属填充材料没有接缝和/或空隙。此外，公开了通过用金属电镀种子层衬里高纵横比开口（例如，高纵横比通孔或沟槽）形成这种电镀金属结构的方法的实施例，然后在其上形成保护层金属电镀种子层的一部分与开口侧壁相邻，使得随后的电镀仅从开口的底表面发生。

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