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1. 发明申请

US20100295132A1 PROGRAMMABLE PN ANTI-FUSE 有权
标题翻译：可编程PN防熔丝
公开(公告)号：US20100295132A1
公开(公告)日：2010-11-25
申请号：US12698302
申请日：2010-02-02
申请人： Ping-Chuan Wang , Robert C. Wong , Haining S. Yang
发明人： Ping-Chuan Wang , Robert C. Wong , Haining S. Yang
IPC分类号： H01L27/06 , H01L21/8234 , H01L21/326
CPC分类号： H01L27/0727 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p− substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p− substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse.
摘要翻译：在FET结构中提供可编程反熔丝的结构和方法。形成可编程反熔丝的方法包括：提供具有n +栅极叠层的p衬底; 在p衬底中注入n +源极区域和n +漏极区域; 在n +漏极区域上形成抗蚀剂掩模，同时使n +源极区域露出; 蚀刻n +源极区域以在n +源极区域中形成凹陷; 以及在n +源极区的凹槽中生长p +外延硅锗层以形成用作可编程二极管或反熔丝的pn结。

2. 发明授权

US08178945B2 Programmable PN anti-fuse 有权
标题翻译：可编程PN反熔丝
公开(公告)号：US08178945B2
公开(公告)日：2012-05-15
申请号：US12698302
申请日：2010-02-02
申请人： Ping-Chuan Wang , Robert C. Wong , Haining S. Yang
发明人： Ping-Chuan Wang , Robert C. Wong , Haining S. Yang
IPC分类号： H01L23/52
CPC分类号： H01L27/0727 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p− substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p− substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse.
摘要翻译：在FET结构中提供可编程反熔丝的结构和方法。形成可编程反熔丝的方法包括：提供具有n +栅极叠层的p衬底; 在p衬底中注入n +源极区域和n +漏极区域; 在n +漏极区域上形成抗蚀剂掩模，同时使n +源极区域露出; 蚀刻n +源极区域以在n +源极区域中形成凹陷; 以及在n +源极区的凹槽中生长p +外延硅锗层以形成用作可编程二极管或反熔丝的pn结。

3. 发明申请

US20090108356A1 INTEGRATION SCHEME FOR MULTIPLE METAL GATE WORK FUNCTION STRUCTURES 失效
标题翻译：多金属门工作功能结构的整合方案
公开(公告)号：US20090108356A1
公开(公告)日：2009-04-30
申请号：US11924053
申请日：2007-10-25
申请人： Kangguo Cheng , Michael P. Chudzik , Rama Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
发明人： Kangguo Cheng , Michael P. Chudzik , Rama Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
IPC分类号： H01L29/78 , H01L21/44
CPC分类号： H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1116 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.
摘要翻译：在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整氧化层。还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

4. 发明申请

US20090026523A1 PARTIALLY GATED FINFET 有权
标题翻译：部分浇注金属
公开(公告)号：US20090026523A1
公开(公告)日：2009-01-29
申请号：US11782079
申请日：2007-07-24
申请人： Robert C. Wong , Haining S. Yang
发明人： Robert C. Wong , Haining S. Yang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1211 , H01L29/785
摘要： A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit.
摘要翻译：在至少一个半导体鳍片的侧壁上形成栅极电介质和栅极导体层。图案化栅极导体层，使得栅极电极形成在半导体鳍片的一部分的第一侧壁上，而在第一侧壁的相对侧上的第二侧壁不受栅电极控制。因此，形成了部分选通的finFET，即在第一侧壁上具有栅电极且在第二侧壁上没有栅电极的finFET。传统的双栅极finFET可以在同一衬底上与本发明的部分选通的鳍状FET形成，以在诸如SRAM电路的同一电路中提供具有不同导通电流的多个finFET。

5. 发明授权

US08432764B2 Boost cell supply write assist 有权
标题翻译：提升电池供应写入协助
公开(公告)号：US08432764B2
公开(公告)日：2013-04-30
申请号：US12778223
申请日：2010-05-12
申请人： Omer Heymann , Dana Bar-Niv , Noam Jungmann , Elazar Kachir , Udi Nir , Limor Plotkin , Amira Rozenfeld , Robert C. Wong , Haining S. Yang
发明人： Omer Heymann , Dana Bar-Niv , Noam Jungmann , Elazar Kachir , Udi Nir , Limor Plotkin , Amira Rozenfeld , Robert C. Wong , Haining S. Yang
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/145
摘要： A method of increasing a drain to source voltage measured at an access pass-gate to a SRAM circuit in a SRAM memory array, including increasing a low voltage from a low voltage source powering said SRAM circuit, and increasing a high voltage from a high voltage source powering the SRAM circuit.
摘要翻译：一种在SRAM存储器阵列中的SRAM电路的访问通过门处测量的漏极到源极电压的增加的方法，包括从为所述SRAM电路供电的低电压源增加低电压，以及从高电压增加高电压来源为SRAM电路供电。

6. 发明申请

US20120126339A1 SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS 有权
标题翻译：栅极电极区域之间具有减少的距离的半导体晶体管
公开(公告)号：US20120126339A1
公开(公告)日：2012-05-24
申请号：US13357757
申请日：2012-01-25
申请人： Robert C. Wong , Haining S. Yang
发明人： Robert C. Wong , Haining S. Yang
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/823437 , H01L21/823475 , H01L27/0207 , Y10S257/903
摘要： A semiconductor structure. The semiconductor structure includes: a semiconductor substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface and further includes a first semiconductor body region and a second semiconductor body region; a first gate dielectric region and a second gate dielectric region on top of the first and second semiconductor body regions, respectively; a first gate electrode region on top of the semiconductor substrate and the first gate dielectric region; a second gate electrode region on top of the semiconductor substrate and the second gate dielectric region; and a gate divider region in direct physical contact with the first and second gate electrode regions. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.
摘要翻译：半导体结构。半导体结构包括：半导体衬底，其包括限定垂直于顶部衬底表面的参考方向的顶部衬底表面，并且还包括第一半导体本体区域和第二半导体本体区域; 分别在第一和第二半导体本体区域的顶部上的第一栅极电介质区域和第二栅极电介质区域; 在所述半导体衬底和所述第一栅极电介质区域的顶部上的第一栅极电极区域; 在所述半导体衬底和所述第二栅极电介质区域的顶部上的第二栅极电极区域; 以及与第一和第二栅电极区域直接物理接触的栅极分压区域。栅极分压器区域在参考方向上不与第一和第二栅电极区域重叠。

7. 发明授权

US07859044B2 Partially gated FINFET with gate dielectric on only one sidewall 有权
标题翻译：部分选通FINFET，仅在一个侧壁上具有栅极电介质
公开(公告)号：US07859044B2
公开(公告)日：2010-12-28
申请号：US11782079
申请日：2007-07-24
申请人： Robert C. Wong , Haining S. Yang
发明人： Robert C. Wong , Haining S. Yang
IPC分类号： H01L29/78 , H01L27/12
CPC分类号： H01L29/66795 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1211 , H01L29/785
摘要： A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit.
摘要翻译：在至少一个半导体鳍片的侧壁上形成栅极电介质和栅极导体层。图案化栅极导体层，使得栅极电极形成在半导体鳍片的一部分的第一侧壁上，而在第一侧壁的相对侧上的第二侧壁不受栅电极控制。因此，形成了部分选通的finFET，即在第一侧壁上具有栅电极且在第二侧壁上没有栅电极的finFET。传统的双栅极finFET可以在同一衬底上与本发明的部分选通的鳍状FET形成，以在诸如SRAM电路的同一电路中提供具有不同导通电流的多个finFET。

8. 发明申请

US20090032886A1 SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS 有权
标题翻译：栅极电极区域之间具有减少的距离的半导体晶体管
公开(公告)号：US20090032886A1
公开(公告)日：2009-02-05
申请号：US11830090
申请日：2007-07-30
申请人： Robert C. Wong , Haining S. Yang
发明人： Robert C. Wong , Haining S. Yang
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/088 , H01L21/823437 , H01L21/823475 , H01L27/0207 , Y10S257/903
摘要： A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) first and second semiconductor body regions. The method further includes forming (i) a gate divider region and (ii) a gate electrode layer on top of the semiconductor substrate. The gate divider region is in direct physical contact with gate electrode layer. A top surface of the gate electrode layer and a top surface of the gate divider region are essentially coplanar. The method further includes patterning the gate electrode layer resulting in a first gate electrode region and a second gate electrode region. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.
摘要翻译：半导体结构及其形成方法。该方法包括提供包括半导体衬底的半导体结构。半导体衬底包括（i）限定垂直于顶部衬底表面的参考方向的顶部衬底表面和（ii）第一和第二半导体本体区域。该方法还包括在半导体衬底的顶部形成（i）栅极分隔区和（ii）栅电极层。栅极分压器区域与栅极电极层直接物理接触。栅电极层的顶表面和栅极分隔区的顶表面基本上是共面的。该方法还包括图案化栅极电极层，形成第一栅电极区域和第二栅电极区域。栅极分压器区域在参考方向上不与第一和第二栅电极区域重叠。

9. 发明授权

US08476717B2 Semiconductor transistors having reduced distances between gate electrode regions 有权
标题翻译：半导体晶体管具有减小栅电极区域之间的距离
公开(公告)号：US08476717B2
公开(公告)日：2013-07-02
申请号：US13357757
申请日：2012-01-25
申请人： Robert C. Wong , Haining S. Yang
发明人： Robert C. Wong , Haining S. Yang
IPC分类号： H01L27/088 , H01L27/118
CPC分类号： H01L27/088 , H01L21/823437 , H01L21/823475 , H01L27/0207 , Y10S257/903
摘要： A semiconductor structure. The semiconductor structure includes: a semiconductor substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface and further includes a first semiconductor body region and a second semiconductor body region; a first gate dielectric region and a second gate dielectric region on top of the first and second semiconductor body regions, respectively; a first gate electrode region on top of the semiconductor substrate and the first gate dielectric region; a second gate electrode region on top of the semiconductor substrate and the second gate dielectric region; and a gate divider region in direct physical contact with the first and second gate electrode regions. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.
摘要翻译：半导体结构。半导体结构包括：半导体衬底，其包括限定垂直于顶部衬底表面的参考方向的顶部衬底表面，并且还包括第一半导体本体区域和第二半导体本体区域; 分别在第一和第二半导体本体区域的顶部上的第一栅极电介质区域和第二栅极电介质区域; 在所述半导体衬底和所述第一栅极电介质区域的顶部上的第一栅极电极区域; 在所述半导体衬底和所述第二栅极电介质区域的顶部上的第二栅极电极区域; 以及与第一和第二栅电极区域直接物理接触的栅极分压区域。栅极分压器区域在参考方向上不与第一和第二栅电极区域重叠。

10. 发明授权

US08173532B2 Semiconductor transistors having reduced distances between gate electrode regions 有权
标题翻译：半导体晶体管具有减小栅电极区域之间的距离
公开(公告)号：US08173532B2
公开(公告)日：2012-05-08
申请号：US11830090
申请日：2007-07-30
申请人： Robert C. Wong , Haining S. Yang
发明人： Robert C. Wong , Haining S. Yang
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/461 , H01L21/8244 , H01L21/302 , H01L27/118 , H01L27/088 , H01L27/11
CPC分类号： H01L27/088 , H01L21/823437 , H01L21/823475 , H01L27/0207 , Y10S257/903
摘要： A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) first and second semiconductor body regions. The method further includes forming (i) a gate divider region and (ii) a gate electrode layer on top of the semiconductor substrate. The gate divider region is in direct physical contact with gate electrode layer. A top surface of the gate electrode layer and a top surface of the gate divider region are essentially coplanar. The method further includes patterning the gate electrode layer resulting in a first gate electrode region and a second gate electrode region. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.
摘要翻译：半导体结构及其形成方法。该方法包括提供包括半导体衬底的半导体结构。半导体衬底包括（i）限定垂直于顶部衬底表面的参考方向的顶部衬底表面和（ii）第一和第二半导体本体区域。该方法还包括在半导体衬底的顶部形成（i）栅极分隔区和（ii）栅电极层。栅极分压器区域与栅极电极层直接物理接触。栅电极层的顶表面和栅极分隔区的顶表面基本上是共面的。该方法还包括图案化栅电极层，形成第一栅电极区和第二栅电极区。栅极分压器区域在参考方向上不与第一和第二栅电极区域重叠。

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