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1. 发明授权

US07365399B2 Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost 有权
标题翻译：用于形成半导体上孔（SOP）的结构和方法，用于高器件性能和低制造成本
公开(公告)号：US07365399B2
公开(公告)日：2008-04-29
申请号：US11333074
申请日：2006-01-17
申请人： Joel P. de Souza , Keith E. Fogel , Brian J. Greene , Devendra K. Sadana , Haining S. Yang
发明人： Joel P. de Souza , Keith E. Fogel , Brian J. Greene , Devendra K. Sadana , Haining S. Yang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/32 , H01L21/0203 , H01L21/76259 , H01L29/1033 , H01L29/1083 , H01L29/16 , H01L29/78
摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.
摘要翻译：提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层。

2. 发明授权

US07842940B2 Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost 有权
标题翻译：用于形成半导体上孔（SOP）的结构和方法，用于高器件性能和低制造成本
公开(公告)号：US07842940B2
公开(公告)日：2010-11-30
申请号：US12062164
申请日：2008-04-03
申请人： Joel P. de Souza , Keith E. Fogel , Brian J. Greene , Devendra K. Sadana , Haining S. Yang
发明人： Joel P. de Souza , Keith E. Fogel , Brian J. Greene , Devendra K. Sadana , Haining S. Yang
IPC分类号： H01L31/00
CPC分类号： H01L29/32 , H01L21/0203 , H01L21/76259 , H01L29/1033 , H01L29/1083 , H01L29/16 , H01L29/78
摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.
摘要翻译：提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层。

3. 发明申请

US20080179712A1 STRUCTURE AND METHOD TO FORM SEMICONDUCTOR-ON-PORES (SOP) FOR HIGH DEVICE PERFORMANCE AND LOW MANUFACTURING COST 有权
标题翻译：用于形成用于高器件性能和低制造成本的半导体器件（SOP）的结构和方法
公开(公告)号：US20080179712A1
公开(公告)日：2008-07-31
申请号：US12062164
申请日：2008-04-03
申请人： Joel P. de Souza , Keith E. Fogel , Brian J. Greene , Devendra K. Sadana , Haining S. Yang
发明人： Joel P. de Souza , Keith E. Fogel , Brian J. Greene , Devendra K. Sadana , Haining S. Yang
IPC分类号： H01L29/06 , H01L21/76
CPC分类号： H01L29/32 , H01L21/0203 , H01L21/76259 , H01L29/1033 , H01L29/1083 , H01L29/16 , H01L29/78
摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.
摘要翻译：提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层。

4. 发明授权

US08217470B2 Field effect device including recessed and aligned germanium containing channel 有权
标题翻译：场效应器件包括凹入和对准的含锗通道
公开(公告)号：US08217470B2
公开(公告)日：2012-07-10
申请号：US12702682
申请日：2010-02-09
申请人： Xiangdong Chen , Brian J. Greene , Haining S. Yang
发明人： Xiangdong Chen , Brian J. Greene , Haining S. Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/28194 , H01L29/1054 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66651
摘要： A field effect structure and a method for fabricating the field effect structure include a germanium containing channel interposed between a plurality of source and drain regions. The germanium containing channel is coplanar with the plurality of source and drain regions, and the germanium containing channel includes a germanium containing material having a germanium content greater than the germanium content of the plurality of source and drain regions.
摘要翻译：场效应结构和用于制造场效应结构的方法包括介于多个源区和漏区之间的含锗通道。含锗通道与多个源极和漏极区域共面，并且含锗沟道包括锗含量大于多个源极和漏极区的锗含量的含锗材料。

5. 发明申请

US20100200934A1 FIELD EFFECT DEVICE INCLUDNG RECESSED AND ALIGNED GERMANIUM CONTAINING CHANNEL 有权
标题翻译：包含被包含和对齐的含有通道的锗的场效应器件
公开(公告)号：US20100200934A1
公开(公告)日：2010-08-12
申请号：US12702682
申请日：2010-02-09
申请人： Xiangdong Chen , Brian J. Greene , Haining S. Yang
发明人： Xiangdong Chen , Brian J. Greene , Haining S. Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/28194 , H01L29/1054 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66651
摘要： A field effect structure and a method for fabricating the field effect structure include a germanium containing channel interposed between a plurality of source and drain regions. The germanium containing channel is coplanar with the plurality of source and drain regions, and the germanium containing channel includes a germanium containing material having a germanium content greater than the germanium content of the plurality of source and drain regions.
摘要翻译：场效应结构和用于制造场效应结构的方法包括介于多个源区和漏区之间的含锗通道。含锗通道与多个源极和漏极区域共面，并且含锗沟道包括锗含量大于多个源极和漏极区的锗含量的含锗材料。

6. 发明授权

US08674444B2 Structure and method of forming a transistor with asymmetric channel and source/drain regions 有权
标题翻译：形成具有不对称沟道和源极/漏极区的晶体管的结构和方法
公开(公告)号：US08674444B2
公开(公告)日：2014-03-18
申请号：US13422297
申请日：2012-03-16
申请人： Haining S. Yang , Kangguo Cheng , Robert Wong
发明人： Haining S. Yang , Kangguo Cheng , Robert Wong
IPC分类号： H01L27/12
CPC分类号： H01L29/78618 , H01L29/78684 , H01L29/78696
摘要： A semiconductor structure includes a semiconductor substrate. A conductive gate abuts a gate insulator for controlling conduction of a channel region. The gate insulator abuts the channel region. A source region and a drain region are associated with the conductive gate. The source region includes a first material and the drain region includes a second material. The conductive gate is self-aligned to the first and the second material.
摘要翻译：半导体结构包括半导体衬底。导电栅极邻接栅极绝缘体，用于控制沟道区的导通。栅极绝缘体邻接沟道区域。源极区域和漏极区域与导电栅极相关联。源极区域包括第一材料，漏极区域包括第二材料。导电栅极与第一和第二材料自对准。

7. 发明授权

US08461625B2 Carrier mobility enhanced channel devices and method of manufacture 有权
标题翻译：载波移动增强信道设备和制造方法
公开(公告)号：US08461625B2
公开(公告)日：2013-06-11
申请号：US13080352
申请日：2011-04-05
申请人： Kangguo Cheng , Haining S. Yang
发明人： Kangguo Cheng , Haining S. Yang
IPC分类号： H01L29/78
CPC分类号： H01L21/823828 , H01L21/823807 , H01L29/7845 , Y10S438/926
摘要： An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material.
摘要翻译：提供了具有应力增强通道的集成电路，设计结构和制造集成电路的方法。该方法包括在衬底上形成虚拟栅极结构并在虚拟栅极结构中形成沟槽。该方法还包括用应变诱导材料填充沟槽的一部分并用栅极材料填充沟槽的剩余部分。

8. 发明授权

US08432764B2 Boost cell supply write assist 有权
标题翻译：提升电池供应写入协助
公开(公告)号：US08432764B2
公开(公告)日：2013-04-30
申请号：US12778223
申请日：2010-05-12
申请人： Omer Heymann , Dana Bar-Niv , Noam Jungmann , Elazar Kachir , Udi Nir , Limor Plotkin , Amira Rozenfeld , Robert C. Wong , Haining S. Yang
发明人： Omer Heymann , Dana Bar-Niv , Noam Jungmann , Elazar Kachir , Udi Nir , Limor Plotkin , Amira Rozenfeld , Robert C. Wong , Haining S. Yang
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/145
摘要： A method of increasing a drain to source voltage measured at an access pass-gate to a SRAM circuit in a SRAM memory array, including increasing a low voltage from a low voltage source powering said SRAM circuit, and increasing a high voltage from a high voltage source powering the SRAM circuit.
摘要翻译：一种在SRAM存储器阵列中的SRAM电路的访问通过门处测量的漏极到源极电压的增加的方法，包括从为所述SRAM电路供电的低电压源增加低电压，以及从高电压增加高电压来源为SRAM电路供电。

9. 发明申请

US20120235236A1 STRUCTURE AND METHOD OF FORMING A TRANSISTOR WITH ASYMMETRIC CHANNEL AND SOURCE/DRAIN REGIONS 有权
标题翻译：用不对称通道和源/漏区形成晶体管的结构和方法
公开(公告)号：US20120235236A1
公开(公告)日：2012-09-20
申请号：US13422297
申请日：2012-03-16
申请人： Haining S. Yang , Kangguo Cheng , Robert Wong
发明人： Haining S. Yang , Kangguo Cheng , Robert Wong
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78618 , H01L29/78684 , H01L29/78696
摘要： A semiconductor structure includes a semiconductor substrate. A conductive gate abuts a gate insulator for controlling conduction of a channel region. The gate insulator abuts the channel region. A source region and a drain region are associated with the conductive gate. The source region includes a first material and the drain region includes a second material. The conductive gate is self-aligned to the first and the second material.
摘要翻译：半导体结构包括半导体衬底。导电栅极邻接栅极绝缘体，用于控制沟道区的导通。栅极绝缘体邻接沟道区域。源极区域和漏极区域与导电栅极相关联。源极区域包括第一材料，漏极区域包括第二材料。导电栅极与第一和第二材料自对准。

10. 发明授权

US08232210B2 Double patterning process for integrated circuit device manufacturing 有权
标题翻译：集成电路器件制造的双重图案化工艺
公开(公告)号：US08232210B2
公开(公告)日：2012-07-31
申请号：US12562222
申请日：2009-09-18
申请人： Kangguo Cheng , Haining S. Yang
发明人： Kangguo Cheng , Haining S. Yang
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/265 , H01L21/28008 , H01L21/32139 , H01L21/76816
摘要： A method of forming an integrated circuit (IC) device feature includes forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned; forming a first photoresist layer over the hardmask layer; patterning a first set of semiconductor device features in the first photoresist layer; registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the first photoresist layer; forming a second photoresist layer over the substantially planar hardmask layer; patterning a second set of semiconductor device features in the second photoresist layer; registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the second photoresist layer; and creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor device features.
摘要翻译：形成集成电路（IC）器件特征的方法包括：在待图案化的半导体器件层上形成初始基本平坦的硬掩模层; 在所述硬掩模层上形成第一光致抗蚀剂层; 图案化第一光致抗蚀剂层中的第一组半导体器件特征; 在硬掩模层中以保持硬掩模层基本上平面的方式对准第一组半导体器件特征; 去除第一光致抗蚀剂层; 在所述基本上平坦的硬掩模层上形成第二光致抗蚀剂层; 在第二光致抗蚀剂层中图形化第二组半导体器件特征; 在硬掩模层中以保持硬掩模层基本上平面的方式对准第二组半导体器件特征; 去除所述第二光致抗蚀剂层; 以及通过移除与所述第一和第二组半导体器件特征对应的部分来在所述硬掩模层内产生形貌。

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