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31. 发明申请

US20120290994A1 TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT 失效
标题翻译：逻辑集成电路的总功率优化
公开(公告)号：US20120290994A1
公开(公告)日：2012-11-15
申请号：US13103461
申请日：2011-05-09
申请人： Benjamin Mbouombouo , Ramnath Venkatraman , Ruggero Castagnetti
发明人： Benjamin Mbouombouo , Ramnath Venkatraman , Ruggero Castagnetti
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/505 , G06F2217/78
摘要： A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.
摘要翻译：减少逻辑单元的总功耗的方法包括：选择对应于至少一个路径的逻辑单元的分布，在逻辑单元的分布中计算每个逻辑单元的动态到静态功率比，并将动态到静态功率比排列每个逻辑单元分成下组，中间组和上组逻辑单元。此外，该方法包括交换逻辑单元的下组和用于重构的中间组逻辑单元的逻辑单元的上组，并验证重构的中间组逻辑单元的路径定时。还提供了使用布尔方程和逻辑单元组来降低总功耗的方法。

32. 发明申请

US20120175683A1 Basic Cell Architecture For Structured ASICs 失效
标题翻译：结构化ASIC的基本单元架构
公开(公告)号：US20120175683A1
公开(公告)日：2012-07-12
申请号：US13424747
申请日：2012-03-20
申请人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
发明人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
IPC分类号： H01L27/105
CPC分类号： H03K19/1735 , G06F2217/64 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L27/11807
摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
摘要翻译：提供了具有多个可固定晶体管的单元的基本单元电路架构，其可配置用于形成逻辑器件以及结构化ASIC内的单端口和双端口存储器件。通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。电路架构可以实现单个单元或多个单元内的晶体管的互连。互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。通过具有形成逻辑电路元件，存储器件或二者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，更能适应现代的SoC。

33. 发明申请

US20120126364A1 MITIGATION OF DETRIMENTAL BREAKDOWN OF A HIGH DIELECTRIC CONSTANT METAL-INSULATOR-METAL CAPACITOR IN A CAPACITOR BANK 有权
标题翻译：电容器中高介电常数金属绝缘体 - 金属电容器的绝缘断开的缓解
公开(公告)号：US20120126364A1
公开(公告)日：2012-05-24
申请号：US12953624
申请日：2010-11-24
申请人： Bonnie E. Weir , Edward B. Harris , Ramnath Venkatraman
发明人： Bonnie E. Weir , Edward B. Harris , Ramnath Venkatraman
IPC分类号： H01L23/52 , H01L21/98
CPC分类号： H01L23/5256 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.
摘要翻译： IC电容器组包括连接到一对导电迹线的多个高k金属 - 绝缘体金属（MIM）电容器。位于一对导电迹线之一的端部上的可熔痕迹形成连接在电源线之间的电容器柱，使得MIM电容器中的电介质的故障导致可熔痕迹至少部分地断开，由此限制了在电容柱。此外，制造IC电容器组的方法包括提供连接到一对导电迹线的多个高k金属 - 绝缘体金属（MIM）电容器，并且在一对导电迹线的端部上定位可熔迹线以形成连接在电源线之间的电容器柱，使得MIM电容器中的电介质的故障导致可熔痕迹至少部分地打开，从而限制电容器柱中的故障电流。

34. 发明申请

US20110051304A1 DEFECTIVITY-IMMUNE TECHNIQUE OF IMPLEMENTING MIM-BASED DECOUPLING CAPACITORS 有权
标题翻译：实现基于MIM的解耦电容器的缺陷免疫技术
公开(公告)号：US20110051304A1
公开(公告)日：2011-03-03
申请号：US12839148
申请日：2010-07-19
申请人： Ramnath Venkatraman , Ruggero Castagnetti
发明人： Ramnath Venkatraman , Ruggero Castagnetti
IPC分类号： H02H9/02 , H03H7/00 , H01L21/00
CPC分类号： H01L27/0629 , H01L27/0805 , H03H7/004 , Y10T29/413
摘要： An integrated circuit power supply decoupling circuit includes a capacitor and a protection circuit. The capacitor has a first terminal and a second terminal. The protection circuit includes a first transistor having a first conduction path, and a second transistor having a second conduction path. One terminal of the first conduction path is connected to the first terminal of the capacitor, and another terminal of the first conduction path is connected to a first power supply rail. One terminal of the second conduction path is connected to the second terminal of the capacitor, and another terminal of the second conduction path is connected to a second power supply rail.
摘要翻译：集成电路电源去耦电路包括电容器和保护电路。电容器具有第一端子和第二端子。保护电路包括具有第一导电路径的第一晶体管和具有第二导电路径的第二晶体管。第一导电路径的一个端子连接到电容器的第一端子，并且第一导电路径的另一个端子连接到第一电源轨道。第二导电路径的一个端子连接到电容器的第二端子，第二导电路径的另一个端子连接到第二电源轨道。

35. 发明申请

US20050047254A1 Design and use of a spacer cell to support reconfigurable memories 有权
标题翻译：间隔单元的设计和使用以支持可重构存储器
公开(公告)号：US20050047254A1
公开(公告)日：2005-03-03
申请号：US10650192
申请日：2003-08-27
申请人： Ramnath Venkatraman , Rugger Castagnetti , Subramanian Ramesh
发明人： Ramnath Venkatraman , Rugger Castagnetti , Subramanian Ramesh
IPC分类号： G11C7/18 , G11C8/00 , G11C8/16 , H01L27/11
CPC分类号： G11C7/18 , G11C8/16 , H01L27/11 , Y10S257/903
摘要： A method and apparatus for reconfiguring a memory array is disclosed. Aspects of the present invention include fabricating the memory array as at least one row of single-port cells up to a first metal layer. A split word line having first and second word lines is coupled to the single-port cells in each row, wherein the first word line is patterned in the first metal layer, and the second word line is patterned in a second metal layer. The split word line is further coupled to a spacer cell in the row. The method and apparatus further include programming the base memory array into custom configurations based on whether the first and second word lines are connected over the spacer cell, or whether the first and second word lines are left unconnected.
摘要翻译：公开了一种用于重新配置存储器阵列的方法和装置。本发明的方面包括将存储器阵列制造为直到第一金属层的至少一行单端口单元。具有第一和第二字线的分割字线被耦合到每行中的单端口单元，其中第一字线在第一金属层中被图案化，并且第二字线被图案化在第二金属层中。分割字线还耦合到行中的间隔单元。所述方法和装置还包括基于第一和第二字线是否连接在间隔单元上，或者第一和第二字线是否不连接，将基本存储器阵列编程成定制配置。

36. 发明申请

US20050047238A1 Reconfigurable memory arrays 有权
公开(公告)号：US20050047238A1
公开(公告)日：2005-03-03
申请号：US10655053
申请日：2003-09-03
申请人： Ruggero Castagnetti , Ramnath Venkatraman , Subramanian Ramesh
发明人： Ruggero Castagnetti , Ramnath Venkatraman , Subramanian Ramesh
IPC分类号： G11C5/02 , G11C7/02 , H01L27/02 , H01L27/105
CPC分类号： G11C5/025 , H01L27/0203 , H01L27/105
摘要： A method and system for reconfiguring a memory array is disclosed. Initially, the cells in the memory array are patterned with substantially the same structure up to a predefined layer. Thereafter, the memory array is reconfigured by patterning the cells above the predefined layer such that a first plurality of cells function as memory cells, and a second plurality of cells are patterned as a dummy row or column that function as a breakpoint for the memory array.

37. 发明授权

US06806551B2 Fuse construction for integrated circuit structure having low dielectric constant dielectric material 有权
标题翻译：具有低介电常数介电材料的集成电路结构的保险丝结构
公开(公告)号：US06806551B2
公开(公告)日：2004-10-19
申请号：US10376401
申请日：2003-02-28
申请人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
发明人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L23/5329 , H01L2224/05022 , H01L2924/01019
摘要： Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.
摘要翻译：保险丝和可选的金属焊盘形成在低k电介质材料结构的层上，其具有衬有导电阻挡材料的第一开口并且被填充以在低k电介质材料的上表面中形成金属互连。电介质层形成在低k电介质材料上方和金属互连之上，并被图案化以形成其中与金属互连连通的第二开口。导电阻挡层形成在与金属互连件接触的该电介质层上，并被图案化以在一些金属互连件之间形成熔丝部分，以及在一个或多个金属互连件上的衬垫。然后在图案化的导电阻挡层上方形成电介质层，以形成每个保险丝上方的窗口，并且图案化以在填充有金属的至少一些导电阻挡衬里上形成开口以形成金属焊盘。

38. 发明授权

US06566171B1 Fuse construction for integrated circuit structure having low dielectric constant dielectric material 有权
标题翻译：具有低介电常数介电材料的集成电路结构的保险丝结构
公开(公告)号：US06566171B1
公开(公告)日：2003-05-20
申请号：US09882404
申请日：2001-06-12
申请人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
发明人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
IPC分类号： H01L2182
CPC分类号： H01L23/5258 , H01L23/5329 , H01L2224/05022 , H01L2924/01019
摘要： Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.
摘要翻译：保险丝和可选的金属焊盘形成在低k电介质材料结构的层上，其具有衬有导电阻挡材料的第一开口并且被填充以在低k电介质材料的上表面中形成金属互连。电介质层形成在低k电介质材料上方和金属互连之上，并被图案化以形成其中与金属互连连通的第二开口。导电阻挡层形成在与金属互连件接触的该电介质层上，并被图案化以在一些金属互连件之间形成熔丝部分，以及在一个或多个金属互连件上的衬垫。然后在图案化的导电阻挡层上方形成电介质层，以形成每个保险丝上方的窗口，并且图案化以在填充有金属的至少一些导电阻挡衬里上形成开口以形成金属焊盘。

39. 发明授权

US06218302B1 Method for forming a semiconductor device 失效
标题翻译：半导体器件形成方法
公开(公告)号：US06218302B1
公开(公告)日：2001-04-17
申请号：US09121068
申请日：1998-07-21
申请人： Gregor Braeckelmann , Ramnath Venkatraman , Matthew Thomas Herrick , Cindy R. Simpson , Robert W. Fiordalice , Dean J. Denning , Ajay Jain , Cristiano Capasso
发明人： Gregor Braeckelmann , Ramnath Venkatraman , Matthew Thomas Herrick , Cindy R. Simpson , Robert W. Fiordalice , Dean J. Denning , Ajay Jain , Cristiano Capasso
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L21/76882 , H01L23/53233 , H01L23/53238 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05181 , H01L2224/05184 , H01L2224/05546 , H01L2224/05567 , H01L2224/05647 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01046 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19043 , H01L2924/00014 , H01L2224/05552 , H01L2924/013 , H01L2924/0105 , H01L2924/01026
摘要： An interconnect (60) is formed overlying a substrate (10). In one embodiment, an adhesion/barrier layer (81), a copper-alloy seed layer (42), and a copper film (43) are deposited overlying the substrate (10), and the substrate (10) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (81), a seed layer (82), a conductive film (83), and a copper-alloy capping film (84) are deposited over the substrate (10) to form an interconnect (92). The deposition and annealing steps can be performed on a common processing platform.
摘要翻译：互连（60）形成在衬底（10）上。在一个实施例中，将覆盖在衬底（10）上的粘合/阻挡层（81），铜合金晶种层（42）和铜膜（43）沉积，并且将衬底（10）退火。在替代实施例中，在衬底上沉积铜膜，并对铜膜进行退火。在另一个实施例中，在基板（10）上沉积粘合/阻挡层（81），种子层（82），导电膜（83）和铜合金封盖膜（84），以形成互连（92）。沉积和退火步骤可以在公共处理平台上进行。

40. 发明申请

US20140028364A1 CRITICAL PATH MONITOR HARDWARE ARCHITECTURE FOR CLOSED LOOP ADAPTIVE VOLTAGE SCALING AND METHOD OF OPERATION THEREOF 审中-公开
标题翻译：闭环自适应电压调节关键路径监测器硬件结构及其运行方法
公开(公告)号：US20140028364A1
公开(公告)日：2014-01-30
申请号：US13560371
申请日：2012-07-27
申请人： Ramnath Venkatraman , Prasad Subbarao , Ruggero Castagnetti
发明人： Ramnath Venkatraman , Prasad Subbarao , Ruggero Castagnetti
IPC分类号： H03K5/14
CPC分类号： G01R31/31725 , G06F1/206 , G06F1/26 , G06F1/3296 , Y02D10/172
摘要： A critical path monitor (CPM), a method of setting supply voltage based on output of a CPM and an integrated circuit (IC) incorporating the CPM. In one embodiment, the CPM includes: (1) an edge detector configured to produce a thermometer output over a plurality of clock cycles and (2) a min_max recorder, coupled to the edge detector and configured to record minimum and maximum values of the thermometer output during a polling interval.
摘要翻译：关键路径监视器（CPM），基于CPM的输出设置电源电压的方法以及包含CPM的集成电路（IC）。在一个实施例中，CPM包括：（1）边缘检测器，被配置为在多个时钟周期内产生温度计输出，以及（2）min_max记录器，耦合到边缘检测器并被配置为记录温度计的最小值和最大值在轮询间隔期间输出。

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