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31. 发明申请

US20130235735A1 DIAGNOSTICS IN A DISTRIBUTED FABRIC SYSTEM 有权
标题翻译：分布式织物系统中的诊断
公开(公告)号：US20130235735A1
公开(公告)日：2013-09-12
申请号：US13414684
申请日：2012-03-07
申请人： Sushma Anantharam , Nirapada Ghosh , Keshav Govind Kamble , Dar-Ren Leu , Chandarani J. Mendon , Nilanjan Mukherjee , Vijoy Pandey , Nandakumar Peethambaram
发明人： Sushma Anantharam , Nirapada Ghosh , Keshav Govind Kamble , Dar-Ren Leu , Chandarani J. Mendon , Nilanjan Mukherjee , Vijoy Pandey , Nandakumar Peethambaram
IPC分类号： H04L12/28 , H04L12/26
CPC分类号： H04L49/356 , H04L41/12 , H04L41/22 , H04L43/045 , H04L43/0811 , H04L43/0817 , H04L49/555
摘要： A distributed fabric system has distributed line card (DLC) chassis and scaled-out fabric coupler (SFC) chassis. Each DLC chassis includes a network processor and fabric ports. Each network processor of each DLC chassis includes a fabric interface in communication with the DLC fabric ports of that DLC chassis. Each SFC chassis includes a fabric element and fabric ports. A communication link connects each SFC fabric port to one DLC fabric port. Each communication link includes cell-carrying lanes. Each fabric element of each SFC chassis collects per-lane statistics for each SFC fabric port of that SFC chassis. Each SFC chassis includes program code that obtains the per-lane statistics collected by the fabric element chip of that SFC chassis. A network element includes program code that gathers the per-lane statistics collected by each fabric element of each SFC chassis and integrates the statistics into a topology of the entire distributed fabric system.
摘要翻译：分布式架构系统具有分布式线卡（DLC）机箱和扩展架构耦合器（SFC）机箱。每个DLC机箱都包括一个网络处理器和Fabric端口。每个DLC机箱的每个网络处理器包括与该DLC机箱的DLC结构端口通信的结构接口。每个SFC机箱都包括一个fabric元素和fabric端口。通信链路将每个SFC Fabric端口连接到一个DLC fabric端口。每个通信链路包括蜂窝载波通道。每个SFC机箱的每个结构元素都会收集该SFC机箱的每个SFC结构端口的每通道统计信息。每个SFC机箱都包含程序代码，用于获取该SFC机箱的结构单元芯片收集的每通道统计信息。网元包括收集每个SFC机箱的每个结构元素收集的每通道统计信息的程序代码，并将统计信息整合到整个分布式系统的拓扑中。

32. 发明授权

US08418007B2 On-chip comparison and response collection tools and techniques 有权
标题翻译：片上比较和响应收集工具和技术
公开(公告)号：US08418007B2
公开(公告)日：2013-04-09
申请号：US13053188
申请日：2011-03-21
申请人： Nilanjan Mukherjee , Janusz Rajski , Jerzy Tyszer
发明人： Nilanjan Mukherjee , Janusz Rajski , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/31723 , G01R31/31727 , G01R31/318547 , G01R31/318563 , G01R31/318566
摘要： Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000x. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
摘要翻译：这里公开了所谓的X压测试响应压实机的示例性实施例。所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。所公开技术的某些实施例提供约1000x的压实比。所公开的压实机的示例性实施例可以保持与传统的基于扫描的测试场景相同的覆盖范围和大约相同的诊断分辨率。扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。

33. 发明授权

US08347159B2 Compression based on deterministic vector clustering of incompatible test cubes 有权
标题翻译：基于不兼容测试立方体的确定性向量聚类的压缩
公开(公告)号：US08347159B2
公开(公告)日：2013-01-01
申请号：US12718813
申请日：2010-03-05
申请人： Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Dariusz Czysz , Jerzy Tyszer
发明人： Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G06F11/00
CPC分类号： G01R31/31921 , G01R31/318547
摘要： The test data compression scheme is based on deterministic vector clustering. Test cubes that feature many similar specified bits are merged into a parent pattern in the presence of conflicts. The parent pattern along with a control pattern and incremental patterns representing conflicting bits are encoded efficiently. A tri-modal decompressor may be used to decompress the test data.
摘要翻译：测试数据压缩方案基于确定性向量聚类。在存在冲突的情况下，具有许多类似指定位的测试立方体将合并到父模式中。父模式以及表示冲突位的控制模式和增量模式被有效地编码。三模式解压缩器可用于解压缩测试数据。

34. 发明申请

US20120210181A1 SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST 有权
标题翻译：用于系统级测试的扫描链的选择性周期性掩蔽
公开(公告)号：US20120210181A1
公开(公告)日：2012-08-16
申请号：US13453929
申请日：2012-04-23
申请人： Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31703 , G01R31/31723 , G01R31/31724 , G01R31/3177 , G01R31/318547 , G06F11/27
摘要： Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
摘要翻译：用于处理未知状态问题的集成电路的内置自检技术。一些实现使用与时间压缩器相连的专用扫描链选择器。专门的扫描链选择器的存在提高了掩蔽X状态的效率。还公开了：（1）与多个扫描链和时间压实器一起工作的选择器的架构，（2）用于确定和编码随后抑制X状态的每个周期扫描链选择掩模的方法，以及（3）以处理过度掩蔽现象。

35. 发明申请

US20110231722A1 ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES 有权
标题翻译：片上比较和响应收集工具和技术
公开(公告)号：US20110231722A1
公开(公告)日：2011-09-22
申请号：US13053188
申请日：2011-03-21
申请人： Nilanjan Mukherjee , Janusz Rajski , Jerzy Tyszer
发明人： Nilanjan Mukherjee , Janusz Rajski , Jerzy Tyszer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/31723 , G01R31/31727 , G01R31/318547 , G01R31/318563 , G01R31/318566
摘要： Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000x. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
摘要翻译：这里公开了所谓的“X-press”测试响应压实机的示例性实施例。所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。所公开技术的某些实施例提供约1000x的压实比。所公开的压实机的示例性实施例可以保持与传统的基于扫描的测试场景相同的覆盖范围和大约相同的诊断分辨率。扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。

36. 发明申请

US20110167309A1 DECOMPRESSOR/PRPG FOR APPLYING PSEUDO-RANDOM AND DETERMINISTIC TEST PATTERNS 审中-公开
标题翻译：适用于伪随机和确定性测试模式的解码器/ PRPG
公开(公告)号：US20110167309A1
公开(公告)日：2011-07-07
申请号：US12983815
申请日：2011-01-03
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318335 , G01R31/31813 , G01R31/318385 , G01R31/318547
摘要： A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.
摘要翻译：微芯片上的新型解压缩器/ PRPG对芯片上的电路不足测试的确定性测试模式进行伪随机测试模式生成和解压缩。解压缩器/ PRPG有两个操作阶段。在伪随机阶段，解压缩器/ PRPG生成伪随机测试图案，其应用于被测电路中的扫描链。在确定性阶段，将外部测试仪的压缩确定性测试模式应用于解压缩器/ PRPG。在通过解压缩器/ PRPG计时到扫描链中时，模式被解压缩。因此，解压缩器/ PRPG提供比简单PRPG更好的故障覆盖，但是没有完整的完整指定的确定性测试模式的成本。

37. 发明申请

US20110138242A1 METHOD AND APPARATUS FOR SELECTIVELY COMPACTING TEST RESPONSES 有权
标题翻译：选择性测试反应的方法和装置
公开(公告)号：US20110138242A1
公开(公告)日：2011-06-09
申请号：US12891498
申请日：2010-09-27
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547
摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.
摘要翻译：一种在确定性测试环境中压缩包含未知值或多个故障效应的测试响应的方法和装置。所提出的选择性压实机采用具有用于选择性地将测试响应传递给压实机的选择电路的线性压实机。在一个实施例中，门控逻辑由控制寄存器，解码器和标志寄存器控制。该电路结合任何常规的并行测试响应压缩方案，允许控制电路选择性地使所需扫描链的串行输出以特定时钟速率馈送到并联压实机。第一个标志寄存器确定是否启用所有或只有一些扫描链输出并通过压实器馈送。第二个标志寄存器确定选择器寄存器选择的扫描链是否启用，所有其他扫描链是禁用的，还是禁用所选扫描链，并启用所有其他扫描链。其他实施例允许对可变数目的扫描链输出的选择性掩蔽。

38. 发明授权

US07865794B2 Decompressor/PRPG for applying pseudo-random and deterministic test patterns 有权
标题翻译：解压缩器/ PRPG用于应用伪随机和确定性测试模式
公开(公告)号：US07865794B2
公开(公告)日：2011-01-04
申请号：US12402880
申请日：2009-03-12
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318335 , G01R31/31813 , G01R31/318385 , G01R31/318547
摘要： A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.
摘要翻译：微芯片上的新型解压缩器/ PRPG对芯片上的电路不足测试的确定性测试模式进行伪随机测试模式生成和解压缩。解压缩器/ PRPG有两个操作阶段。在伪随机阶段，解压缩器/ PRPG生成伪随机测试图案，其应用于被测电路中的扫描链。在确定性阶段，将外部测试仪的压缩确定性测试模式应用于解压缩器/ PRPG。在通过解压缩器/ PRPG计时到扫描链中时，模式被解压缩。因此，解压缩器/ PRPG提供比简单PRPG更好的故障覆盖，但是没有完整的完整指定的确定性测试模式的成本。

39. 发明授权

US07533309B2 Testing memories using algorithm selection 有权
标题翻译：使用算法选择测试记忆
公开(公告)号：US07533309B2
公开(公告)日：2009-05-12
申请号：US10861851
申请日：2004-06-04
申请人： Nilanjan Mukherjee , Joseph C. Rayhawk , Amrendra Kumar
发明人： Nilanjan Mukherjee , Joseph C. Rayhawk , Amrendra Kumar
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/10 , G11C29/14 , G11C29/16 , G11C29/38 , G11C2029/3202
摘要： A method of performing a built-in-self-test (BIST) of at least one memory element of a circuit is disclosed. In a specific example, a determination is made during running of a BIST whether one or more algorithms are to be run. If any algorithm is not designated for running, the particular algorithm is skipped and the test moves to other algorithms to be run. A BIST controller is configured to perform a group of test algorithms. Certain algorithms from the group may be checked to see if they are to be run or bypassed. A delay or skip state is desirably interposed following the inclusion of a particular algorithm and prior to the start of a next algorithm. A determination is made during the delay or skip state whether the next algorithm is to be run. The user may also have the option of running all of the algorithms if desired for performance of a particular BIST.
摘要翻译：公开了一种执行电路的至少一个存储元件的内置自检（BIST）的方法。在具体示例中，在BIST的运行期间确定是否要运行一个或多个算法。如果没有指定运算的算法，跳过特定的算法，并且测试移动到要运行的其他算法。 BIST控制器被配置为执行一组测试算法。可以检查组中的某些算法，以查看它们是要运行还是旁路。期望在包含特定算法之后并且在下一个算法开始之前插入延迟或跳过状态。在延迟或跳过状态期间确定是否要运行下一个算法。如果需要执行特定的BIST，用户还可以选择运行所有算法。

40. 发明授权

US07493540B1 Continuous application and decompression of test patterns to a circuit-under-test 有权
标题翻译：将测试模式连续应用和解压缩到被测电路
公开(公告)号：US07493540B1
公开(公告)日：2009-02-17
申请号：US09620021
申请日：2000-07-20
申请人： Jansuz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Jansuz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/31813 , G01R31/318335
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.
摘要翻译：在测试电路中将测试图案应用于扫描链的方法。该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。执行解压缩的电路包括解压缩器，例如适于接收压缩的位测试模式的线性有限状态机。解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。电路还包括用于测试电路逻辑的扫描链，扫描链耦合到解压缩器并且适于接收解压缩的测试图案。

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