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1. 发明授权

US07493540B1 Continuous application and decompression of test patterns to a circuit-under-test 有权
标题翻译：将测试模式连续应用和解压缩到被测电路
公开(公告)号：US07493540B1
公开(公告)日：2009-02-17
申请号：US09620021
申请日：2000-07-20
申请人： Jansuz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Jansuz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/31813 , G01R31/318335
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.
摘要翻译：在测试电路中将测试图案应用于扫描链的方法。该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。执行解压缩的电路包括解压缩器，例如适于接收压缩的位测试模式的线性有限状态机。解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。电路还包括用于测试电路逻辑的扫描链，扫描链耦合到解压缩器并且适于接收解压缩的测试图案。

2. 发明授权

US08024387B2 Method for synthesizing linear finite state machines 有权
标题翻译：线性有限状态机的合成方法
公开(公告)号：US08024387B2
公开(公告)日：2011-09-20
申请号：US11894393
申请日：2007-08-20
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G06F7/58
CPC分类号： G06F7/584 , G06F2207/583 , H03K3/84
摘要： Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.
摘要翻译：用于合成诸如线性反馈移位寄存器（LFSR）或细胞自动机（CA）的高性能线性有限状态机（LFSM）的方法和装置。给定电路的特征多项式，该方法获得原始的LFSM电路，如I型或II型LFSR。然后确定原始电路内的反馈连接。随后，可以以使原始电路的特性保留在修改的LFSM电路中的方式来应用移动反馈连接的多个变换。特别地，如果原始电路由原始特征多项式表示，则该方法保留修改电路中原始电路的最大长度特性，并使修改电路能够产生与原始电路相同的m序列。通过各种转换，可以创建一个修改后的LFSM电路，通过较短的反馈连接线路提供更高的性能，更低的逻辑电平和更低的内部扇出。

3. 发明申请

US20110214026A1 CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES 有权
标题翻译：测试模式的连续应用和分解以及测试响应的选择性压缩
公开(公告)号：US20110214026A1
公开(公告)日：2011-09-01
申请号：US13013712
申请日：2011-01-25
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G06F11/25
CPC分类号： G01R31/318547
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
摘要翻译：在测试电路中将测试图案应用于扫描链的方法。该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。执行解压缩的电路包括解压缩器，例如适于接收压缩的位测试模式的线性有限状态机。解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。

4. 发明申请

US20050097419A1 Method and apparatus for selectively compacting test reponses 有权
标题翻译：用于选择性压实测试报告的方法和设备
公开(公告)号：US20050097419A1
公开(公告)日：2005-05-05
申请号：US10973522
申请日：2004-10-25
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/28 , G01R31/3185 , H01L21/822 , H01L27/04 , G06F11/00
CPC分类号： G01R31/318547
摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.
摘要翻译：一种在确定性测试环境中压缩包含未知值或多个故障效应的测试响应的方法和装置。所提出的选择性压实机采用具有用于选择性地将测试响应传递给压实机的选择电路的线性压实机。在一个实施例中，门控逻辑由控制寄存器，解码器和标志寄存器控制。该电路结合任何常规的并行测试响应压缩方案，允许控制电路选择性地使所需扫描链的串行输出以特定时钟速率馈送到并联压实机。第一个标志寄存器确定是否启用所有或只有一些扫描链输出并通过压实器馈送。第二个标志寄存器确定选择器寄存器选择的扫描链是否启用，所有其他扫描链是禁用的，还是禁用所选扫描链，并启用所有其他扫描链。其他实施例允许对可变数目的扫描链输出的选择性掩蔽。

5. 发明授权

US06829740B2 Method and apparatus for selectively compacting test responses 有权
标题翻译：用于选择性压实测试响应的方法和装置
公开(公告)号：US06829740B2
公开(公告)日：2004-12-07
申请号：US10354576
申请日：2003-01-29
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R3128
CPC分类号： G01R31/318547
摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.
摘要翻译：一种在确定性测试环境中压缩包含未知值或多个故障效应的测试响应的方法和装置。所提出的选择性压实机采用具有用于选择性地将测试响应传递给压实机的选择电路的线性压实机。在一个实施例中，门控逻辑由控制寄存器，解码器和标志寄存器控制。该电路结合任何常规的并行测试响应压缩方案，允许控制电路选择性地使所需扫描链的串行输出以特定时钟速率馈送到并联压实机。第一个标志寄存器确定是否启用所有或只有一些扫描链输出并通过压实器馈送。第二个标志寄存器确定选择器寄存器选择的扫描链是否启用，所有其他扫描链是禁用的，还是禁用所选扫描链，并启用所有其他扫描链。其他实施例允许对可变数目的扫描链输出的选择性掩蔽。

6. 发明授权

US07900104B2 Test pattern compression for an integrated circuit test environment 有权
标题翻译：用于集成电路测试环境的测试模式压缩
公开(公告)号：US07900104B2
公开(公告)日：2011-03-01
申请号：US12405409
申请日：2009-03-17
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/318371 , G01R31/318547
摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.
摘要翻译：一种用于压缩被测电路中扫描链应用的测试图案的方法。该方法包括生成与扫描链内的扫描单元相关联的符号表达式。通过将变量分配给提供给被测电路的外部输入通道上的位来创建符号表达式。使用符号仿真，将变量应用于解压缩器以获取符号表达式。使用确定性模式创建测试立方体，该模式为扫描单元分配值以测试集成电路中的故障。通过将测试立方体中的分配值与与相应扫描单元相关联的符号表达式进行等价来表示一组方程式。求解等式以获得压缩测试图案。

7. 发明授权

US07877656B2 Continuous application and decompression of test patterns to a circuit-under-test 有权
标题翻译：将测试模式连续应用和解压缩到被测电路
公开(公告)号：US07877656B2
公开(公告)日：2011-01-25
申请号：US12352994
申请日：2009-01-13
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/31813 , G01R31/318547
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear feedbackstate machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.
摘要翻译：在测试电路中将测试图案应用于扫描链的方法。该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。执行解压缩的电路包括解压缩器，例如适于接收压缩的比特测试模式的线性反馈状态机。解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。电路还包括用于测试电路逻辑的扫描链，扫描链耦合到解压缩器并适于接收解压缩的测试图案。

8. 发明申请

US20090228749A1 METHOD AND APPARATUS FOR SELECTIVELY COMPACTING TEST RESPONSES 有权
标题翻译：选择性测试反应的方法和装置
公开(公告)号：US20090228749A1
公开(公告)日：2009-09-10
申请号：US12396377
申请日：2009-03-02
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547
摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.
摘要翻译：一种在确定性测试环境中压缩包含未知值或多个故障效应的测试响应的方法和装置。所提出的选择性压实机采用具有用于选择性地将测试响应传递给压实机的选择电路的线性压实机。在一个实施例中，门控逻辑由控制寄存器，解码器和标志寄存器控制。该电路结合任何常规的并行测试响应压缩方案，允许控制电路选择性地使所需扫描链的串行输出以特定时钟速率馈送到并联压实机。第一个标志寄存器确定是否启用所有或只有一些扫描链输出并通过压实器馈送。第二个标志寄存器确定选择器寄存器选择的扫描链是否启用，所有其他扫描链是禁用的，还是禁用所选扫描链，并启用所有其他扫描链。其他实施例允许对可变数目的扫描链输出的选择性掩蔽。

9. 发明授权

US07509546B2 Test pattern compression for an integrated circuit test environment 有权
公开(公告)号：US07509546B2
公开(公告)日：2009-03-24
申请号：US11523111
申请日：2006-09-18
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G06F11/00
CPC分类号： G01R31/318335 , G01R31/318371 , G01R31/318547
摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

10. 发明授权

US07478296B2 Continuous application and decompression of test patterns to a circuit-under-test 有权
标题翻译：将测试模式连续应用和解压缩到被测电路
公开(公告)号：US07478296B2
公开(公告)日：2009-01-13
申请号：US10354633
申请日：2003-01-29
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/31813 , G01R31/318547
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear feedbackstate machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.
摘要翻译：在测试电路中将测试图案应用于扫描链的方法。该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。执行解压缩的电路包括解压缩器，例如适于接收压缩的比特测试模式的线性反馈状态机。解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。电路还包括用于测试电路逻辑的扫描链，扫描链耦合到解压缩器并且适于接收解压缩的测试图案。

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