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1. 发明申请

WO2011116145A1 TEST SCHEDULING AND TEST ACCESS IN TEST COMPRESSION ENVIRONMENT 审中-公开
标题翻译：测试压缩环境中的测试调度和测试访问
公开(公告)号：WO2011116145A1
公开(公告)日：2011-09-22
申请号：PCT/US2011/028741
申请日：2011-03-16
申请人： MENTOR GRAPHICS CORPORATION , KASSAB, Mark, A. , GRZEGORZ, Mrugalski , MUKHERJEE, Nilanjan , RAJSKI, Janusz , JAKUB, Janicki , JERZY, Tyszer
发明人： KASSAB, Mark, A. , GRZEGORZ, Mrugalski , MUKHERJEE, Nilanjan , RAJSKI, Janusz , JAKUB, Janicki , JERZY, Tyszer
IPC分类号： G01R31/319
CPC分类号： G01R31/2834 , G01R31/2851 , G01R31/318335 , G01R31/318547 , G01R31/31921
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.
摘要翻译：公开了测试压缩环境中用于测试调度和测试访问的方法，装置和系统的代表性实施例。基于包括压缩测试数据，对应的测试仪通道要求和相关核心的测试信息形成用于测试电路中的多个核心的测试模式的集群。测试模式集群的形成之后是测试者信道分配。可以采用最佳拟合方案或平衡拟合方案来产生信道分配信息。可以基于信道分配信息来设计用于动态信道分配的测试接入电路。

2. 发明授权

US08046653B2 Low power decompression of test cubes 有权
标题翻译：测试立方体的低功率减压
公开(公告)号：US08046653B2
公开(公告)日：2011-10-25
申请号：US12854786
申请日：2010-08-11
申请人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
发明人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31921 , G01R31/318335
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
摘要翻译：以下公开了用于产生用于测试集成电路的测试图案的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）环境）集成。所公开的技术的某些实施例可以在没有硬件修改的情况下降低扫描链中的开关速率，从而降低功耗。其他实施例使用专门的减压硬件和压缩技术来实现低功率测试。

3. 发明授权

US08024387B2 Method for synthesizing linear finite state machines 有权
标题翻译：线性有限状态机的合成方法
公开(公告)号：US08024387B2
公开(公告)日：2011-09-20
申请号：US11894393
申请日：2007-08-20
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G06F7/58
CPC分类号： G06F7/584 , G06F2207/583 , H03K3/84
摘要： Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.
摘要翻译：用于合成诸如线性反馈移位寄存器（LFSR）或细胞自动机（CA）的高性能线性有限状态机（LFSM）的方法和装置。给定电路的特征多项式，该方法获得原始的LFSM电路，如I型或II型LFSR。然后确定原始电路内的反馈连接。随后，可以以使原始电路的特性保留在修改的LFSM电路中的方式来应用移动反馈连接的多个变换。特别地，如果原始电路由原始特征多项式表示，则该方法保留修改电路中原始电路的最大长度特性，并使修改电路能够产生与原始电路相同的m序列。通过各种转换，可以创建一个修改后的LFSM电路，通过较短的反馈连接线路提供更高的性能，更低的逻辑电平和更低的内部扇出。

4. 发明申请

US20110214026A1 CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES 有权
标题翻译：测试模式的连续应用和分解以及测试响应的选择性压缩
公开(公告)号：US20110214026A1
公开(公告)日：2011-09-01
申请号：US13013712
申请日：2011-01-25
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G06F11/25
CPC分类号： G01R31/318547
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
摘要翻译：在测试电路中将测试图案应用于扫描链的方法。该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。执行解压缩的电路包括解压缩器，例如适于接收压缩的位测试模式的线性有限状态机。解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。

5. 发明申请

US20110166818A1 LOW POWER SCAN TESTING TECHNIQUES AND APPARATUS 有权
标题翻译：低功耗扫描测试技术和设备
公开(公告)号：US20110166818A1
公开(公告)日：2011-07-07
申请号：US13049844
申请日：2011-03-16
申请人： Xijiang Lin , Dariusz Czysz , Mark Kassab , Grzegorz Mrugalski , Janusz Rajski , Jerzy Tyszer
发明人： Xijiang Lin , Dariusz Czysz , Mark Kassab , Grzegorz Mrugalski , Janusz Rajski , Jerzy Tyszer
IPC分类号： G06F19/00
CPC分类号： G01R31/318575
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.
摘要翻译：以下公开了用于在集成电路测试期间降低功耗的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）架构）集成。在所公开的实施例中，具有可编程测试刺激选择器，可编程扫描使能电路，可编程时钟使能电路，可编程移位使能电路和/或可编程复位使能电路的集成电路。还公开了可以用于产生用于与任何所公开的实施例一起使用的测试图案的示例性测试图形生成方法。

6. 发明申请

US20100083063A1 PHASE SHIFTER WITH REDUCED LINEAR DEPENDENCY 有权
标题翻译：具有减少线性关系的相位变换器
公开(公告)号：US20100083063A1
公开(公告)日：2010-04-01
申请号：US12633601
申请日：2009-12-08
申请人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
发明人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318541 , G01R31/31813 , G01R31/318385 , G01R31/318547 , G01R31/318594
摘要： A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.
摘要翻译：公开了用于自动合成移相器的方法，该移相器用于消除驱动并行扫描链的伪随机测试图形发生器所特征的结构依赖性的影响。使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

7. 发明授权

US07647540B2 Decompressors for low power decompression of test patterns 有权
标题翻译：减压器用于低功耗减压测试图案
公开(公告)号：US07647540B2
公开(公告)日：2010-01-12
申请号：US11880192
申请日：2007-07-19
申请人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
发明人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G01R31/28 , G06F11/00 , G06F17/50 , G06G7/48
CPC分类号： G01R31/318547 , G01R31/318335
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
摘要翻译：以下公开了用于产生用于测试集成电路的测试图案的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）环境）集成。所公开的技术的某些实施例可以在没有硬件修改的情况下降低扫描链中的开关速率，从而降低功耗。其他实施例使用专门的减压硬件和压缩技术来实现低功率测试。

8. 发明申请

US20090187800A1 PHASE SHIFTER WITH REDUCED LINEAR DEPENDENCY 有权
标题翻译：具有减少线性关系的相位变换器
公开(公告)号：US20090187800A1
公开(公告)日：2009-07-23
申请号：US12412267
申请日：2009-03-26
申请人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
发明人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318541 , G01R31/31813 , G01R31/318385 , G01R31/318547 , G01R31/318594
摘要： A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.
摘要翻译：公开了用于自动合成移相器的方法，该移相器用于消除驱动并行扫描链的伪随机测试图形发生器所特征的结构依赖性的影响。使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

9. 发明申请

US20070300110A1 Phase shifter with reduced linear dependency 有权
标题翻译：移相器具有减少的线性依赖性
公开(公告)号：US20070300110A1
公开(公告)日：2007-12-27
申请号：US11895845
申请日：2007-08-27
申请人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
发明人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
IPC分类号： G01R31/3183 , G06F11/26
CPC分类号： G01R31/318541 , G01R31/31813 , G01R31/318385 , G01R31/318547 , G01R31/318594
摘要： A method is disclosed for the automated synthesis of phase shifters. Phase shifters comprise circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.
摘要翻译：公开了用于自动合成移相器的方法。移相器包括用于消除驱动并行扫描链的伪随机测试图形发生器特征的结构依赖性的影响的电路。使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

10. 发明授权

US07302624B2 Adaptive fault diagnosis of compressed test responses 有权
标题翻译：压缩测试响应的自适应故障诊断
公开(公告)号：US07302624B2
公开(公告)日：2007-11-27
申请号：US11213327
申请日：2005-08-25
申请人： Janusz Rajski , Grzegorz Mrugalski , Artur Pogiel , Jerzy Tyszer , Chen Wang
发明人： Janusz Rajski , Grzegorz Mrugalski , Artur Pogiel , Jerzy Tyszer , Chen Wang
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/31703 , G01R31/318536 , G01R31/318566 , G01R31/318583 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/3202
摘要： Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, one or more signatures are received that indicate the presence of one or more errors in one or more corresponding compressed test responses. Scan cells in the circuit-under-test that caused the errors are identified by analyzing the signatures. In this exemplary embodiment, the analysis includes selecting a scan cell candidate that potentially caused an error in a compressed test response based at least partially on a weight value associated with the scan cell candidate, the weight value being indicative of the likelihood that the scan cell candidate caused the error. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.
摘要翻译：本文公开了用于诊断来自压缩测试响应的故障扫描单元的方法，装置和系统。例如，在一个非限制性示例性实施例中，接收指示在一个或多个对应的压缩测试响应中存在一个或多个错误的一个或多个签名。通过分析签名来识别导致错误的电路不足测试中的扫描单元。在该示例性实施例中，分析包括选择至少部分地基于与扫描小区候选者相关联的权重值来潜在地引起压缩测试响应中的错误的扫描小区候选，该权重值表示扫描单元候选人造成错误。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的有形计算机可读介质。还提供了包括由任何所公开的方法识别的故障扫描单元的列表的有形计算机可读介质。

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